JPS55133561A - Method of fabricating lead frame for semiconductor - Google Patents

Method of fabricating lead frame for semiconductor

Info

Publication number
JPS55133561A
JPS55133561A JP4016679A JP4016679A JPS55133561A JP S55133561 A JPS55133561 A JP S55133561A JP 4016679 A JP4016679 A JP 4016679A JP 4016679 A JP4016679 A JP 4016679A JP S55133561 A JPS55133561 A JP S55133561A
Authority
JP
Japan
Prior art keywords
lead frame
metal
resist
positive image
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4016679A
Other languages
Japanese (ja)
Other versions
JPS6024583B2 (en
Inventor
Kanichi Iimori
Takao Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP4016679A priority Critical patent/JPS6024583B2/en
Publication of JPS55133561A publication Critical patent/JPS55133561A/en
Publication of JPS6024583B2 publication Critical patent/JPS6024583B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To shorten the steps of fabricating the lead frame for a semiconductor by forming a resist having a positive image excluding the bonded portion on the front surface of a metal plate and a resist having a positive image on the back surface of the plate, semi-etching the metal plate at the bonded portion and then plating metal thereon. CONSTITUTION:The first resist 2 having a positive image excluding a portion to be bonded by a metal plating to a lead frame is formed on the front surface of a metal plate 1 made of Cu, Ni, Cr or the like, and a second resist 3 having a positive image of the lead frame is formed on the back surface of the metal plate 1. The exposed portion is etched and removed, the metal plated portion to be bonded is semi-etched, rinsed with water, and then plated with bonding metal 5 such as Au, Ag or the like. The first and second resists 2, 3 are then separated to complete the lead frame. Thus, it eliminates the steps of mounting a plating jig and degreasing it to shorten the steps and also enhances the matching step of the portions to be plated.
JP4016679A 1979-04-03 1979-04-03 Manufacturing method for semiconductor lead frames Expired JPS6024583B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4016679A JPS6024583B2 (en) 1979-04-03 1979-04-03 Manufacturing method for semiconductor lead frames

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4016679A JPS6024583B2 (en) 1979-04-03 1979-04-03 Manufacturing method for semiconductor lead frames

Publications (2)

Publication Number Publication Date
JPS55133561A true JPS55133561A (en) 1980-10-17
JPS6024583B2 JPS6024583B2 (en) 1985-06-13

Family

ID=12573171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4016679A Expired JPS6024583B2 (en) 1979-04-03 1979-04-03 Manufacturing method for semiconductor lead frames

Country Status (1)

Country Link
JP (1) JPS6024583B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61279698A (en) * 1985-06-05 1986-12-10 Hitachi Cable Ltd Production of lead frame having microspot plating part
JPH01261852A (en) * 1988-04-12 1989-10-18 Fuji Plant Kogyo Kk Method of partially plating lead frame
KR100530754B1 (en) * 1998-09-09 2006-02-28 삼성테크윈 주식회사 Method of continuously manufacturing a lead frame
JP2010010634A (en) * 2008-06-30 2010-01-14 Shinko Electric Ind Co Ltd Lead frame, and method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61279698A (en) * 1985-06-05 1986-12-10 Hitachi Cable Ltd Production of lead frame having microspot plating part
JPH01261852A (en) * 1988-04-12 1989-10-18 Fuji Plant Kogyo Kk Method of partially plating lead frame
KR100530754B1 (en) * 1998-09-09 2006-02-28 삼성테크윈 주식회사 Method of continuously manufacturing a lead frame
JP2010010634A (en) * 2008-06-30 2010-01-14 Shinko Electric Ind Co Ltd Lead frame, and method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS6024583B2 (en) 1985-06-13

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