JP2009545879A - 応力注入マスクに基づく応力メモライゼーションにより歪みトランジスタを形成する方法 - Google Patents
応力注入マスクに基づく応力メモライゼーションにより歪みトランジスタを形成する方法 Download PDFInfo
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Abstract
Description
当然のことながら、そのような現実の実施品の開発においては、開発者における特定の目標を達成するため、システム的制限やビジネス的制限との摺り合せなど、多くの特定の実施の決定がなされる。それらは各実施形態によって様々に変化するものである。更に、そのような開発努力は複雑で時間を消費するものであるのは当然のことであるが、それでもなお、この開示の恩恵を有する当業者にとっては通常作業の範疇に入るものである。
これにより、エッチマスク325に基づいてマスク層319から適切なスペーサ素子が形成され、その後、第1トランジスタ350Aにそれぞれの深いドレインおよびソース領域を形成するように、それぞれの注入プロセスを実行してもよい。
Claims (14)
- 半導体層(103)内の、第1導電型のドーパント種を受け入れるとともに第1ゲート電極(105A)に隣接する第1領域を、特定の第1の固有応力を含む第1の注入マスク(109)により覆うステップと、
第2ゲート電極(105B)に隣接するとともに前記第1注入マスク(109)には覆われていない第2領域に、第2導電型のドーパント種を注入するステップと、
前記第1注入マスク(109)が配置された前記第1および第2領域をアニーリングするステップと、を含む方法。 - 前記注入マスク(109)を形成するために、レジストマスク(110)に基づいて応力材料層を形成し、前記応力材料層をパターニングするステップをさらに含む、請求項1記載の方法。
- 前記レジストマスク(110)は、前記第2導電型の前記ドーパント種の注入時に維持される、請求項2記載の方法。
- 前記応力材料層の上方に、レジスト材料に対して表面の接着性が増加した層(108)を形成し、さらに、前記表面の接着性が増加した層(108)の上方にレジスト層(110)を蒸着するステップをさらに含む、請求項2記載の方法。
- 前記注入マスク(109)を除去するステップをさらに含む、請求項1記載の方法。
- 第2の固有応力を含む第2注入マスクを形成するステップを含み、前記第2注入マスクは前記第2領域を覆うとともに前記第1領域は露出されるものであって、前記第1導電型の前記ドーパント種を前記露出した第1領域に注入するステップと、前記第2注入マスクの少なくとも応力のかけられた部分がある場合に前記第1領域をアニーリングするステップと、をさらに含む、請求項1記載の方法。
- 前記第2注入マスクは、前記第1導電型の前記ドーパント種が前記第1領域に受け入れられる前に形成される、請求項6記載の方法。
- 第1の固有応力を有する第1注入マスク(219)により第2トランジスタ(250B)を覆うとともに、第1ドーパント種を第1トランジスタ(250A)に導入するステップと、
前記第1注入マスク(219)が配置された前記第1および第2トランジスタ(205A、205B)をアニーリングするステップと、を含む、方法。 - 応力材料層を形成するステップ、
レジスト材料を受け入れるために前記応力材料層の上方に、表面接着性が増加した層(218)を形成するステップ、および、
前記レジスト材料から形成したレジストマスク(225)に基づいて前記第1の注入マスク(219)をパターニングするステップ、
を含む請求項8記載の方法。 - 前記第1ドーパント種を導入するときに前記レジストマスク(225)が維持される、請求項9記載の方法。
- 第2の固有応力を含む第2の注入マスク(209)を形成するステップをさらに含み、前記第2の注入マスク(209)は、前記第2トランジスタ(250B)を露出させ、前記第1トランジスタ(205A)を覆い、前記第2トランジスタ(205B)に第2のドーパント種を導入し、前記第1および第2トランジスタ(205A、205B)を、少なくとも応力のかけられた部分がある場合にアニーリングする、請求項8記載の方法。
- 第1トランジスタ(250A)を露出させて第2トランジスタ(250B)を覆うように、第1の種類の固有応力を有する第1注入マスク(219)を形成するステップと、
前記第1の注入マスク(219)に基づいて前記第1トランジスタ(250A)に第1ドーパント種を導入するステップと、
前記第1注入マスクが配置された第2トランジスタをアニーリングするステップと、
前記第1トランジスタ(250A)を覆い、前記第2トランジスタ(250B)を露出するように、第2の種類の固有応力を有する第2の注入マスク(209)を形成するステップと、
前記第2の注入マスク(209)に基づいて前記第2トランジスタ(250B)に第2ドーパント種を導入するステップと、
前記第2の注入マスク(209)が配置された第1トランジスタ(250A)をアニーリングするステップと、を含む方法。 - 前記第1の種類の固有応力は引張応力であり、前記第2の種類の固有応力は圧縮応力である、請求項12記載の方法。
- 前記第1の種類の固有応力は圧縮応力であり、前記第2の種類の固有応力は引張応力である、請求項12記載の方法。
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DE200610035646 DE102006035646B3 (de) | 2006-07-31 | 2006-07-31 | Verfahren zur Herstellung verformter Transistoren durch Verspannungskonservierung auf der Grundlage einer verspannten Implantationsmaske |
US11/746,106 US7964458B2 (en) | 2006-07-31 | 2007-05-09 | Method for forming a strained transistor by stress memorization based on a stressed implantation mask |
PCT/US2007/016579 WO2008016505A1 (en) | 2006-07-31 | 2007-07-24 | Method for forming a strained transistor by stress memorization based on a stressed implantation mask |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014168024A (ja) * | 2013-02-28 | 2014-09-11 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2017028307A (ja) * | 2016-10-05 | 2017-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2017224864A (ja) * | 2017-09-21 | 2017-12-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006051494B4 (de) * | 2006-10-31 | 2009-02-05 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur, die einen Feldeffekt-Transistor mit verspanntem Kanalgebiet umfasst |
DE102007030056B3 (de) * | 2007-06-29 | 2009-01-22 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Blockieren einer Voramorphisierung einer Gateelektrode eines Transistors |
DE102007057687B4 (de) * | 2007-11-30 | 2010-07-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen einer Zugverformung in Transistoren |
US20090179308A1 (en) * | 2008-01-14 | 2009-07-16 | Chris Stapelmann | Method of Manufacturing a Semiconductor Device |
DE102008007003B4 (de) * | 2008-01-31 | 2015-03-19 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zum selektiven Erzeugen von Verformung in einem Transistor durch eine Verspannungsgedächtnistechnik ohne Hinzufügung weiterer Lithographieschritte |
DE102008011928B4 (de) * | 2008-02-29 | 2010-06-02 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Herstellen eines Halbleiterbauelements unter Verwendung einer Ätzstoppschicht mit geringerer Dicke zum Strukturieren eines dielektrischen Materials |
DE102008016426B4 (de) * | 2008-03-31 | 2012-04-19 | Globalfoundries Inc. | Verfahren zum Erzeugen einer Zugverformung durch Anwenden von Verspannungsgedächtnistechniken in unmittelbarer Nähe zu der Gateelektrode |
US7833888B2 (en) * | 2008-05-06 | 2010-11-16 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system employing grain size enlargement |
DE102008026132A1 (de) * | 2008-05-30 | 2009-12-10 | Advanced Micro Devices, Inc., Sunnyvale | Durchlassstromeinstellung für Transistoren, die in dem gleichen aktiven Gebiet gebildet sind, durch lokales Hervorrufen unterschiedlicher lateraler Verformungspegel in dem aktiven Gebiet |
US20090302401A1 (en) * | 2008-06-05 | 2009-12-10 | Chartered Semiconductor Manufacturing, Ltd. | Pfet enhancement during smt |
DE102008046400B4 (de) * | 2008-06-30 | 2011-05-19 | Amd Fab 36 Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines CMOS-Bauelements mit MOS-Transistoren mit abgesenkten Drain- und Sourcebereichen und einem Si/Ge-Material in den Drain- und Sourcebereichen des PMOS-Transistors |
DE102009006801B4 (de) * | 2009-01-30 | 2011-05-19 | Amd Fab 36 Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines Feldeffekt-Kurzkanaltransistors mit geringerer Längenfluktuation durch Verwenden eines amorphen Elektrodenmaterials während der Implantation |
US8236709B2 (en) * | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
CN102201369B (zh) * | 2010-03-22 | 2014-03-19 | 中芯国际集成电路制造(上海)有限公司 | 一种制作具有应力层的互补金属氧化物半导体器件的方法 |
DE102010028462B4 (de) * | 2010-04-30 | 2015-06-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen |
CN102420138A (zh) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的制作方法 |
CN102468160A (zh) * | 2010-11-03 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | 利用应力记忆技术提高nfet窄沟道效应的方法 |
US8617955B2 (en) * | 2011-07-12 | 2013-12-31 | Varian Semiconductor Equipment Associates, Inc. | Method and system for forming low contact resistance device |
CN102543875A (zh) * | 2011-11-02 | 2012-07-04 | 上海华力微电子有限公司 | 一种在半导体器件中应用应力记忆技术的方法 |
US20130149820A1 (en) * | 2011-12-12 | 2013-06-13 | Chien-Chung Huang | Method for manufacturing semiconductor device |
CN103545257A (zh) * | 2012-07-12 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos晶体管的制作方法 |
US9041076B2 (en) * | 2013-02-03 | 2015-05-26 | International Business Machines Corporation | Partial sacrificial dummy gate with CMOS device with high-k metal gate |
KR102143431B1 (ko) * | 2013-12-06 | 2020-08-28 | 삼성전자주식회사 | 불순물 영역 형성 방법 및 반도체 소자의 제조 방법 |
FR3023411B1 (fr) * | 2014-07-07 | 2017-12-22 | Commissariat Energie Atomique | Generation localisee de contrainte dans un substrat soi |
CN106898550B (zh) * | 2015-12-21 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法、电子装置 |
KR102414957B1 (ko) | 2018-06-15 | 2022-06-29 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
CN111370313B (zh) * | 2020-04-27 | 2023-08-18 | 上海华力微电子有限公司 | Nmos器件的制备方法 |
CN116206980A (zh) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | 半导体器件的制作方法以及半导体器件 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004282068A (ja) * | 2003-03-12 | 2004-10-07 | Samsung Electronics Co Ltd | 半導体装置の形成方法 |
US20060073650A1 (en) * | 2004-09-24 | 2006-04-06 | Seetharaman Sridhar | Method to selectively strain NMOS devices using a cap poly layer |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4068746B2 (ja) * | 1998-12-25 | 2008-03-26 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US7279746B2 (en) | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
US8008724B2 (en) * | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
US20050136583A1 (en) * | 2003-12-23 | 2005-06-23 | Taiwan Semiconductor Manufacturing Co. | Advanced strained-channel technique to improve CMOS performance |
US7052946B2 (en) * | 2004-03-10 | 2006-05-30 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method for selectively stressing MOSFETs to improve charge carrier mobility |
US7316960B2 (en) | 2004-07-13 | 2008-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhanced ultra shallow junction formation |
US7223647B2 (en) | 2004-11-05 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company | Method for forming integrated advanced semiconductor device using sacrificial stress layer |
US20060099765A1 (en) * | 2004-11-11 | 2006-05-11 | International Business Machines Corporation | Method to enhance cmos transistor performance by inducing strain in the gate and channel |
DE102006046381B4 (de) * | 2006-09-29 | 2009-08-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Verringerung der "Lackvergiftung" während der Strukturierung verspannter stickstoffenthaltender Schichten in einem Halbleiterbauelement |
-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004282068A (ja) * | 2003-03-12 | 2004-10-07 | Samsung Electronics Co Ltd | 半導体装置の形成方法 |
US20060073650A1 (en) * | 2004-09-24 | 2006-04-06 | Seetharaman Sridhar | Method to selectively strain NMOS devices using a cap poly layer |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014168024A (ja) * | 2013-02-28 | 2014-09-11 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2017028307A (ja) * | 2016-10-05 | 2017-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2017224864A (ja) * | 2017-09-21 | 2017-12-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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CN101517731A (zh) | 2009-08-26 |
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US7964458B2 (en) | 2011-06-21 |
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