JP2004282068A - 半導体装置の形成方法 - Google Patents
半導体装置の形成方法 Download PDFInfo
- Publication number
- JP2004282068A JP2004282068A JP2004069814A JP2004069814A JP2004282068A JP 2004282068 A JP2004282068 A JP 2004282068A JP 2004069814 A JP2004069814 A JP 2004069814A JP 2004069814 A JP2004069814 A JP 2004069814A JP 2004282068 A JP2004282068 A JP 2004282068A
- Authority
- JP
- Japan
- Prior art keywords
- type
- gate pattern
- forming
- pattern
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000012535 impurity Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims description 51
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 230000007547 defect Effects 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- -1 arsenic ions Chemical class 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】
半導体基板上にそれぞれN型ゲートパターン110a及びP型ゲートパターン110bを形成する。N型トランジスタ形成領域に選択的にN型不純物を注入し、その後、前記N型ゲートパターン、P型ゲートパターン及び基板表面上に第1絶縁膜120を蒸着する。次いで、前記N型トランジスタ形成領域には前記第1絶縁膜120aをそのまま残し、P型トランジスタ形成領域には前記第1絶縁膜を異方性食刻して前記P型ゲートパターン110bの側面に選択的に第1スペーサを形成する。そして、前記P型ゲートパターン110b及び第1スペーサが形成された前記P型トランジスタ形成領域に選択的にP型不純物を注入してCMOSトランジスタを形成する。従って、エッチングダメージによるトランジスタの特性低下を最小化することができる。
【選択図】 図7
Description
110a N型ゲートパターン、
110b P型ゲートパターン、
116 N型LDD領域、
120 第1絶縁膜、
122 フォトレジストパターン、
130 第1スペーサ、
134 P型LDD領域。
Claims (21)
- i)半導体基板上で区分されるN型トランジスタ形成領域及びP型トランジスタ形成領域に、それぞれN型ゲートパターン及びP型ゲートパターンを形成する段階と、
ii)前記N型トランジスタ形成領域に選択的にN型不純物を注入する段階と、
iii)前記N型ゲートパターン、前記P型ゲートパターン、及び前記基板表面上に第1絶縁膜を蒸着する段階と、
iv)前記N型トランジスタ形成領域では前記第1絶縁膜をそのまま残し、前記P型トランジスタ形成領域では前記第1絶縁膜を異方性食刻して前記P型ゲートパターンの側面に選択的に第1スペーサを形成する段階と、
v)前記P型ゲートパターンと第1スペーサとが形成された前記P型トランジスタ形成領域に選択的にP型不純物を注入する段階と、を含むことを特徴とする半導体装置の形成方法。 - 前記i)段階の前記N型ゲートパターン及びP型ゲートパターンは、ゲート絶縁膜パターンと非ドーピングのポリシリコン膜パターンとが積層された形態を有することを特徴とする請求項1記載の半導体装置の形成方法。
- 前記i)段階を実施した後に、前記N型ゲートパターン、前記P型ゲートパターン、及び前記基板表面に欠陥を修復するための酸化膜を形成する段階を含むことを特徴とする請求項1記載の半導体装置の形成方法。
- 前記ii)段階は、
前記N型トランジスタ形成領域を選択的に露出する第1フォトレジストパターンを形成する段階と、
前記第1フォトレジストパターンをイオン注入マスクとして用いて前記N型ゲートパターン及び露出された基板表面下にN型不純物を注入することで、前記N型ゲートパターンを導電性のN型ゲートパターンとするとともに、N型低濃度ドーピング領域を形成する段階と、
前記第1フォトレジストパターンを除去する段階と、を含むことを特徴とする請求項1記載の半導体装置の形成方法。 - 前記ii)段階においてN型不純物は砒素Asを含むことを特徴とする請求項1記載の半導体装置の形成方法。
- 前記第1絶縁膜はシリコン窒化膜からなることを特徴とする請求項1記載の半導体装置の形成方法。
- 前記第1絶縁膜は650乃至800℃の温度条件で形成されることを特徴とする請求項1記載の半導体装置の形成方法。
- 前記第1絶縁膜は160乃至240Åの厚さに形成されることを特徴とする請求項1記載の半導体装置の形成方法。
- 前記iv)段階は、
前記P型トランジスタ形成領域を選択的に露出する第2フォトレジストパターンを形成する段階と、
前記第2フォトレジストパターンをエッチングマスクとして用いて前記P型トランジスタ形成領域に蒸着された前記第1絶縁膜を選択的に異方性食刻して、前記P型ゲートパターン側面に第1スペーサを形成する段階と、を含むことを特徴とする請求項1記載の半導体装置の形成方法。 - 前記v)段階は、
前記第2フォトレジストパターンをイオン注入マスクとして用いて前記P型ゲートパターン及び露出された基板表面下にP型不純物を注入して、前記P型ゲートパターンを導電性のP型ゲートパターンとするとともに、P型低濃度ドーピング領域を形成する段階と、
前記第2フォトレジストパターンを除去する段階と、を含むことを特徴とする請求項9記載の半導体装置の形成方法。 - 前記v)段階のP型不純物はホウ素Bを含むことを特徴とする請求項1記載の半導体装置の形成方法。
- 前記v)段階を実施した後に、
前記N型トランジスタ形成領域に残されている前記第1絶縁膜及び前記P型トランジスタ形成領域の第1スペーサを選択的に除去する段階と、
前記N型ゲートパターン及びP型ゲートパターンのそれぞれの側面に第2スペーサを形成する段階と、
前記N型ゲートパターン及び第2スペーサが形成された前記N型トランジスタ形成領域とに選択的にN型不純物を注入する段階と、
前記P型ゲートパターン及び第2スペーサが形成された前記P型トランジスタ形成領域に選択的にP型不純物を注入する段階と、をさらに含むことを特徴とする請求項1記載の半導体装置の形成方法。 - 前記第1絶縁膜及び第1スペーサは湿式エッチング工程により除去することを特徴とする請求項12記載の半導体装置の形成方法。
- 前記第1絶縁膜及び第1スペーサを除去するためのエッチング液は燐酸H3PO4を含むことを特徴とする請求項13記載の半導体装置の形成方法。
- 前記N型不純物は燐または砒素であることを特徴とする請求項12記載の半導体装置の形成方法。
- i)半導体基板上に区分されるN型トランジスタ形成領域及びP型トランジスタ形成領域に、ゲート絶縁膜パターンと非ドーピングポリシリコン膜パターンとが積層された形態を有するN型ゲートパターン及びP型ゲートパターンをそれぞれ形成する段階と、
ii)前記N型ゲートパターン、前記P型ゲートパターン、及び前記基板表面に欠陥を修復するための熱酸化膜を形成する段階と、
iii)前記N型トランジスタ形成領域に選択的にN型不純物を注入して、前記N型ゲートパターンに含まれる前記ポリシリコンパターンをN型不純物でドーピングするとともに、前記N型ゲートパターンの両側の露出された基板下にN型低濃度ドーピング領域を形成する段階と、
iv)前記N型ゲートパターン、前記P型ゲートパターン、及び基板表面上に第1絶縁膜を蒸着する段階と、
v)前記N型トランジスタ形成領域では前記第1絶縁膜をそのまま残し、前記P型トランジスタ形成領域では前記第1絶縁膜を異方性食刻して前記P型ゲートパターンの側面に選択的に第1スペーサを形成する段階と、
vi)前記P型ゲートパターン及び第1スペーサが形成されたP型トランジスタ形成領域に選択的にP型不純物を注入して、前記P型ゲートパターンに含まれる前記ポリシリコンパターンをP型不純物でドーピングするとともに、前記第1スペーサ両側の露出された基板下にP型低濃度ドーピング領域を形成する段階と、を含むことを特徴とする半導体装置の形成方法。 - 前記第1絶縁膜はシリコン窒化膜からなることを特徴とする請求項16記載の半導体装置の形成方法。
- 前記第1絶縁膜は160乃至240Åの厚さに形成することを特徴とする請求項16記載の半導体装置の形成方法。
- 前記v)段階は、
前記P型トランジスタ形成領域を選択的に露出するフォトレジストパターンを形成する段階と、
前記フォトレジストパターンをエッチングマスクとして用いて前記P型トランジスタ形成領域に蒸着された前記第1絶縁膜を選択的に異方性食刻して、前記P型ゲートパターン側面に第1スペーサを形成する段階と、を含むことを特徴とする請求項16記載の半導体装置の形成方法。 - 前記vi)段階は、
前記フォトレジストパターンをイオン注入マスクとして用いて前記P型ゲートパターン及び露出された基板表面下にP型不純物を注入する段階と、
前記フォトレジストパターンを除去する段階と、を含むことを特徴とする請求項19記載の半導体装置の形成方法。 - 前記vi)段階を実施した後に、
前記N型トランジスタ形成領域に残されている前記第1絶縁膜及び前記P型トランジスタ形成領域の第1スペーサを選択的に除去する段階と、
前記N型ゲートパターン及びP型ゲートパターンのそれぞれの側面に第2スペーサを形成する段階と、
前記N型ゲートパターン及び第2スペーサが形成された前記N型トランジスタ形成領域に選択的にN型不純物を注入してN型高濃度ドーピング領域を形成する段階と、
前記P型ゲートパターン及び第2スペーサが形成された前記P型トランジスタ形成領域に選択的にP型不純物を注入してP型高濃度ドーピング領域を形成する段階と、を含むことを特徴とする請求項16記載の半導体装置の形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0015315A KR100508756B1 (ko) | 2003-03-12 | 2003-03-12 | 반도체 장치의 트랜지스터 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004282068A true JP2004282068A (ja) | 2004-10-07 |
JP4489467B2 JP4489467B2 (ja) | 2010-06-23 |
Family
ID=32960200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004069814A Expired - Fee Related JP4489467B2 (ja) | 2003-03-12 | 2004-03-11 | 半導体装置の形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7067370B2 (ja) |
JP (1) | JP4489467B2 (ja) |
KR (1) | KR100508756B1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191267A (ja) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | Cmos半導体装置の製造方法 |
JP2006294877A (ja) * | 2005-04-11 | 2006-10-26 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
JP2008300505A (ja) * | 2007-05-30 | 2008-12-11 | Renesas Technology Corp | 半導体装置の製造方法 |
US7541234B2 (en) | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
JP2009545879A (ja) * | 2006-07-31 | 2009-12-24 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 応力注入マスクに基づく応力メモライゼーションにより歪みトランジスタを形成する方法 |
US9570362B2 (en) | 2014-05-08 | 2017-02-14 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor device and semiconductor device |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7157343B2 (en) * | 2004-04-07 | 2007-01-02 | United Microelectronics Corp. | Method for fabricating semiconductor device |
US7858458B2 (en) * | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7575975B2 (en) * | 2005-10-31 | 2009-08-18 | Freescale Semiconductor, Inc. | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer |
US7615806B2 (en) * | 2005-10-31 | 2009-11-10 | Freescale Semiconductor, Inc. | Method for forming a semiconductor structure and structure thereof |
KR20080020194A (ko) * | 2006-08-31 | 2008-03-05 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
US20080124830A1 (en) * | 2006-11-29 | 2008-05-29 | Sang-Gi Lee | Method of manufacturing image sensor |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
KR100861218B1 (ko) * | 2007-06-26 | 2008-09-30 | 주식회사 동부하이텍 | 플래시 메모리 소자의 제조 방법 |
DE102007030020B4 (de) * | 2007-06-29 | 2009-03-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden einer Halbleiterstruktur mit einem Ausbilden von mindestens einer Seitenwandabstandshalterstruktur |
US10998443B2 (en) * | 2016-04-15 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epi block structure in semiconductor product providing high breakdown voltage |
CN108630740B (zh) * | 2017-03-16 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015595A (en) * | 1988-09-09 | 1991-05-14 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask |
KR100203131B1 (ko) * | 1996-06-24 | 1999-06-15 | 김영환 | 반도체 소자의 초저접합 형성방법 |
KR19990057380A (ko) | 1997-12-29 | 1999-07-15 | 김영환 | 모스 전계효과 트랜지스터의 제조방법 |
-
2003
- 2003-03-12 KR KR10-2003-0015315A patent/KR100508756B1/ko not_active IP Right Cessation
-
2004
- 2004-02-24 US US10/785,268 patent/US7067370B2/en not_active Expired - Fee Related
- 2004-03-11 JP JP2004069814A patent/JP4489467B2/ja not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191267A (ja) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | Cmos半導体装置の製造方法 |
JP2006294877A (ja) * | 2005-04-11 | 2006-10-26 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
US7541234B2 (en) | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
JP2009545879A (ja) * | 2006-07-31 | 2009-12-24 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 応力注入マスクに基づく応力メモライゼーションにより歪みトランジスタを形成する方法 |
KR101367349B1 (ko) | 2006-07-31 | 2014-02-26 | 글로벌파운드리즈 인크. | 스트레스드 주입 마스크를 기반으로 하여 스트레스 기억에 의해 스트레인드 트랜지스터를 형성하는 방법 |
JP2008300505A (ja) * | 2007-05-30 | 2008-12-11 | Renesas Technology Corp | 半導体装置の製造方法 |
US9570362B2 (en) | 2014-05-08 | 2017-02-14 | Canon Kabushiki Kaisha | Method for manufacturing semiconductor device and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US7067370B2 (en) | 2006-06-27 |
KR20040080510A (ko) | 2004-09-20 |
US20040180504A1 (en) | 2004-09-16 |
JP4489467B2 (ja) | 2010-06-23 |
KR100508756B1 (ko) | 2005-08-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7718506B2 (en) | Isolation structure for MOS transistor and method for forming the same | |
JP4489467B2 (ja) | 半導体装置の形成方法 | |
TW201605045A (zh) | 半導體器件以及其製造方法 | |
US6403425B1 (en) | Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide | |
US7045429B2 (en) | Method of manufacturing a semiconductor device | |
US6261912B1 (en) | Method of fabricating a transistor | |
US5747852A (en) | LDD MOS transistor with improved uniformity and controllability of alignment | |
US20090096023A1 (en) | Method for manufacturing semiconductor device | |
US20040180483A1 (en) | Method of manufacturing CMOS transistor with LDD structure | |
JP5060002B2 (ja) | 半導体装置の製造方法 | |
US7217625B2 (en) | Method of fabricating a semiconductor device having a shallow source/drain region | |
US20070105295A1 (en) | Method for forming lightly-doped-drain metal-oxide-semiconductor (LDD MOS) device | |
KR100370128B1 (ko) | 반도체 소자의 제조방법 | |
US8178932B2 (en) | Semiconductor device having transistors | |
US6232162B1 (en) | Method of complementary metal-oxide semiconductor | |
KR20050009482A (ko) | 반도체 소자의 제조방법 | |
KR100702833B1 (ko) | 고속 트랜지스터의 제조방법 | |
KR100900152B1 (ko) | 반도체 소자의 제조 방법 | |
KR100264211B1 (ko) | 반도체장치의 제조 방법 | |
KR100458770B1 (ko) | 반도체 소자의 제조 방법 | |
KR100566942B1 (ko) | 질화측벽 식각 후 폴리 피팅을 방지하는 트랜지스터제조방법 | |
US20060166442A1 (en) | Method for manufacturing semiconductor device | |
KR100967485B1 (ko) | 반도체 소자 및 반도체 소자의 제조 방법 | |
KR20030001750A (ko) | 반도체 소자의 제조방법 | |
KR20030051037A (ko) | 반도체 소자의 게이트 전극 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060309 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080804 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091020 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100119 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100309 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100331 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130409 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140409 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |