JP2009283921A - 半導体装置及び半導体装置の作製方法 - Google Patents
半導体装置及び半導体装置の作製方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 301
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims description 125
- 238000000034 method Methods 0.000 claims description 28
- 239000012212 insulator Substances 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000010408 film Substances 0.000 abstract description 125
- 239000010409 thin film Substances 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 201
- 239000000758 substrate Substances 0.000 description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 230000008034 disappearance Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
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- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
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- 238000004544 sputter deposition Methods 0.000 description 2
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Abstract
【解決手段】第1の半導体層102の上にゲート絶縁膜103を介して形成されたゲート電極104と、前記ゲート電極の側面に形成されたサイドウォール201と、該サイドウォールの端部202と、前記第1の半導体層102上に接して積層された第2の半導体層106と、を有し、前記第2の半導体層106は前記サイドウォールの端部202の少なくとも一部を覆って形成されている。
【選択図】図2
Description
本実施の形態1では、半導体装置の素子構造の一について説明する。
実施の形態2では、実施の形態1とは異なる半導体装置の素子構造について説明する。
実施の形態3では、半導体装置を作製する第1の方法について図5〜7を用いて説明する。
実施の形態4では、半導体装置を作製する第2の方法について図8、9を用いて説明する。
実施の形態5では、半導体装置を作製する第3の方法について図10、11を用いて説明する。
実施の形態6では、半導体装置を作製する第4の方法について図12を用いて説明する。
本実施の形態においては、開示した半導体装置を用いて作製した電子機器等の例について説明する。
102 第1の半導体層
103 ゲート絶縁膜
104 ゲート電極
105 サイドウォール
106 第2の半導体層
107 チャネル形成領域
108 低濃度不純物領域
109 高濃度不純物領域
110 層間絶縁膜
111 コンタクトホール
112 コンタクトホール
113 電極
114 電極
201 サイドウォール
202 端部
203 幅
301 サイドウォール
302 絶縁層
401 サイドウォール
402 ゲート絶縁膜
501 絶縁膜
502 絶縁膜
601 半導体膜
602 レジストマスク
603 第2の半導体層
701 高濃度不純物領域
702 低濃度不純物領域
703 高濃度不純物領域
801 導電膜
802 絶縁膜
803 ゲート絶縁膜
804 ゲート電極
805 絶縁層
806 絶縁膜
901 サイドウォール
902 第2の半導体層
1001 レジストマスク
1002 サイドウォール
1003 端部
1004 幅
1005 半導体膜
1101 レジストマスク
1102 第2の半導体層
1103 高濃度不純物領域
1105 高濃度不純物領域
1104 低濃度不純物領域
1201 半導体膜
1202 レジストマスク
1203 第2の半導体層
1301〜1305 本体
1311〜1315 表示部
1400〜1407 非接触タグ
Claims (10)
- 絶縁物上に形成された第1の半導体層と、
前記第1の半導体層上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記ゲート電極の側面に接し、端部が前記第1の半導体層上に延伸されたサイドウォールと、
前記第1の半導体層に接して積層され、かつ前記サイドウォールの端部の少なくとも一部に接し又は覆って形成された第2の半導体層と、
を有することを特徴とする半導体装置。 - 絶縁物上に形成された第1の半導体層と、
前記第1の半導体層上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記ゲート電極の側面に接し、端部が前記第1の半導体層上に延伸されたサイドウォールと、
前記第1の半導体層に接して積層され、かつ前記サイドウォールの端部の少なくとも一部に接し又は該一部を覆って形成された第2の半導体層と、
を有し、
前記第1の半導体層には、前記ゲート電極と重なる領域にチャネル形成領域が形成されており、前記サイドウォールと重なる領域には低濃度不純物領域が形成されており、
前記第2の半導体層には、高濃度不純物領域が形成されていることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記ゲート絶縁膜の上面は、前記サイドウォールに接していることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1の半導体層の上面は、前記サイドウォールに接していることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
第2の半導体層と積層する第1の半導体層には、高濃度不純物領域が形成されていることを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一に記載の半導体装置を備えたことを特徴とする電子機器。
- 絶縁物上に第1の半導体層を形成し、
前記第1の半導体層上に順に積層するゲート絶縁膜及びゲート電極を形成し、
前記ゲート電極をマスクとして、前記第1の半導体層に導電性を付与する不純物元素を添加して低濃度不純物領域を形成し、
前記ゲート電極の側面に接し、端部が前記第1の半導体層上に延伸するサイドウォールを形成し、
前記ゲート電極と、前記サイドウォールと、前記サイドウォールの端部と、前記第1の半導体層と、を覆って第2の半導体膜を形成し、
レジストマスクを用いて前記第2の半導体体膜をエッチングして、前記第1の半導体層に接して積層し、かつ前記端部の少なくとも一部に接し又は該一部を覆って、2つの第2の半導体層を形成し、
前記2つの第2の半導体層に導電性を付与する不純物元素を添加して高濃度不純物領域を形成することを特徴とする半導体装置の作製方法。 - 絶縁物上に第1の半導体層を形成し、
前記第1の半導体層上に順に積層するゲート絶縁膜、ゲート電極、絶縁層を形成し、
前記ゲート電極をマスクとして、前記第1の半導体層に導電性を付与する不純物元素を添加して低濃度不純物領域を形成し、
前記ゲート電極の側面にサイドウォールを形成し、
前記絶縁層と、前記サイドウォールと、前記第1の半導体層と、を覆って第2の半導体膜を形成し、
前記第2の半導体膜を覆ってネガ型レジストを形成し、
前記ネガ型レジストに、前記ゲート電極をマスクとして前記絶縁物の裏面側から露光を行ってレジストマスクを形成し、
前記レジストマスクを用いて前記第2の半導体膜をエッチングし、
前記エッチングされた第2の半導体膜をパターニングして、前記第1の半導体層に接して積層し、かつ前記サイドウォールの一部に接し又は該一部を覆って、2つの第2の半導体層を形成し、
前記2つの第2の半導体層に導電性を付与する不純物元素を添加して高濃度不純物領域を形成することを特徴とする半導体装置の作製方法。 - 請求項7又は請求項8において、
前記ゲート絶縁膜の上面は、前記サイドウォールに接するように形成することを特徴とする半導体装置の作製方法。 - 請求項7又は請求項8において、
前記第1の半導体層の上面は、前記サイドウォールに接するように形成することを特徴とする半導体装置の作製方法。
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JP2013168639A (ja) * | 2012-01-20 | 2013-08-29 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2013251536A (ja) * | 2012-05-02 | 2013-12-12 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
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US7772054B2 (en) * | 2007-06-15 | 2010-08-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
KR101084261B1 (ko) * | 2010-03-17 | 2011-11-16 | 삼성모바일디스플레이주식회사 | 박막 트랜지스터, 이를 구비한 표시 장치, 및 그 제조 방법들 |
US8673426B2 (en) * | 2011-06-29 | 2014-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit |
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JP2013168639A (ja) * | 2012-01-20 | 2013-08-29 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
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US10326026B2 (en) | 2012-01-20 | 2019-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2013251536A (ja) * | 2012-05-02 | 2013-12-12 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
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KR101586632B1 (ko) | 2016-01-19 |
JP5503895B2 (ja) | 2014-05-28 |
US8227302B2 (en) | 2012-07-24 |
KR20090113203A (ko) | 2009-10-29 |
US20090267151A1 (en) | 2009-10-29 |
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