JP2009267398A - スタンピング加工を用いて形成される形状を有する半導体素子パッケージ - Google Patents

スタンピング加工を用いて形成される形状を有する半導体素子パッケージ Download PDF

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JP2009267398A
JP2009267398A JP2009091309A JP2009091309A JP2009267398A JP 2009267398 A JP2009267398 A JP 2009267398A JP 2009091309 A JP2009091309 A JP 2009091309A JP 2009091309 A JP2009091309 A JP 2009091309A JP 2009267398 A JP2009267398 A JP 2009267398A
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Prior art keywords
die
die pad
pin
semiconductor device
pins
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JP2009267398A5 (enExample
Inventor
Anthony C Tsui
シー.ツイ アンソニー
Mohammad Eslamy
エスラミー モハンマド
Anthony Chia
チア アンソニー
Hongbo Yang
ヤン ホンボ
Zhou Ming
チョウ ミン
Jian Xu
スー ジアン
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GEM Services Inc USA
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GEM Services Inc USA
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Publication of JP2009267398A publication Critical patent/JP2009267398A/ja
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Lead Frames For Integrated Circuits (AREA)
JP2009091309A 2008-04-04 2009-04-03 スタンピング加工を用いて形成される形状を有する半導体素子パッケージ Pending JP2009267398A (ja)

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US20140167237A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power module package
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US9576884B2 (en) * 2013-03-09 2017-02-21 Adventive Ipbank Low profile leaded semiconductor package
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DE102013211089B4 (de) * 2013-06-14 2025-05-15 Robert Bosch Gmbh Substrat mit einem Bereich zur Begrenzung eines Lotbereichs und Verfahren zu dessen Herstellung
US9627305B2 (en) * 2013-07-11 2017-04-18 Infineon Technologies Ag Semiconductor module with interlocked connection
CN103594448A (zh) * 2013-11-15 2014-02-19 杰群电子科技(东莞)有限公司 一种引线框架
US10134670B2 (en) 2015-04-08 2018-11-20 International Business Machines Corporation Wafer with plated wires and method of fabricating same
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
JP6621681B2 (ja) * 2016-02-17 2019-12-18 株式会社三井ハイテック リードフレーム及びその製造方法、並びに半導体パッケージ
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
US10867894B2 (en) * 2018-10-11 2020-12-15 Asahi Kasei Microdevices Corporation Semiconductor element including encapsulated lead frames
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