JP2009267398A - スタンピング加工を用いて形成される形状を有する半導体素子パッケージ - Google Patents
スタンピング加工を用いて形成される形状を有する半導体素子パッケージ Download PDFInfo
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- JP2009267398A JP2009267398A JP2009091309A JP2009091309A JP2009267398A JP 2009267398 A JP2009267398 A JP 2009267398A JP 2009091309 A JP2009091309 A JP 2009091309A JP 2009091309 A JP2009091309 A JP 2009091309A JP 2009267398 A JP2009267398 A JP 2009267398A
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- die
- die pad
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- pins
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims description 80
- 230000008569 process Effects 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 230000008878 coupling Effects 0.000 claims description 18
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- 238000004080 punching Methods 0.000 claims description 10
- 230000002265 prevention Effects 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000007480 spreading Effects 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims description 3
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- 239000011159 matrix material Substances 0.000 description 8
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
【解決手段】ピン208などのリードフレームの一部はスタンピング加工によってダイパッド204の水平面から押し出される。スタンピング加工によってピン208とダイパッド204の一方もしくは両方の一部に、窪み204a、208aを、あるいは、面取り型などの複雑な横断面外形を付与することができる。こうしたスタンピング加工による横断面外形によって与えられる複雑性は、パッケージボディのプラスチック成形内部でリードフレームの機械的噛み合わせを強める役割を果たす。
【選択図】図2C
Description
本特許出願は、すべての点で参照されその内容全体を本明細書に組み入れられる、2008年4月4日に出願された、米国特許仮出願第61/042,602号の優先権を主張する。
Claims (37)
- 半導体素子のためのパッケージを作製する製法であって、
金属層を設ける工程と、
ダイパッドと複数のピンを画定するために前記金属層をパンチング加工によって貫いて穴のパターンをなす工程と、
形状を作るために前記金属層の一部をスタンピング加工する工程と、
パッケージボディ内部に前記形状の少なくとも一部を封入する工程と、
を含む製法。 - 前記スタンピング加工がダイパッドの一部もしくはピンの一部に窪みを形成する工程をさらに含むことを特徴とする、請求項1に記載の製法。
- 前記スタンピング加工によってピンの一部を前記ダイパッドの水平面の上方に持ち上げることを特徴とする、請求項1に記載の製法。
- 前記スタンピング加工によってピンに、正方形や長方形を除く複雑な横断面外形を付与することを特徴とする、請求項1に記載の製法。
- 前記複雑な横断面外形によって前記パッケージボディ内部のピンを機械的に噛み合わせることを特徴とする、請求項4に記載の製法。
- 前記複雑な横断面外形が、面取り型、砂時計型、T字型、I字型、凹型、凸型、もしくは鋸歯型から選択される、請求項4に記載の製法。
- 前記スタンピング加工によって前記ダイパッドの外周に隣接した穴を作ることを特徴とする、請求項1に記載の製法。
- ダウンボンド・ランウェイ領域が前記ダイパッドの穴と縁の間に画定されることを特徴とする、請求項7に記載の製法。
- 前記パンチング加工によって0.15mm以上の幅を示す複数のピンを作ることを特徴とする、請求項1に記載の製法。
- 前記パンチング加工によって0.4mm以上の間隔幅を有する複数のピンを作ることを特徴とする、請求項1に記載の製法。
- 前記金属層を設ける工程が銅ロールを設ける工程を含むことを特徴とする、請求項1に記載の製法。
- 前記銅ロールを設ける工程が約0.004〜0.020インチの間の厚さを有する銅ロールを設ける工程を含むことを特徴とする、請求項11に記載の製法。
- 前記ピンの一部に電気めっきを施す工程をさらに含むことを特徴とする、請求項1に記載の製法。
- 前記ダイパッドのダイ取付部に電気めっきを施す工程をさらに含むことを特徴とする、請求項13に記載の製法。
- ダイ取付面の周囲に防止帯を形成するために電気めっきされた前記ダイパッドを酸化する工程をさらに含むことを特徴とする、請求項14に記載の製法。
- 電気伝導性接着材料を用いてダイを前記ダイパッドに取付る工程をさらに含むことを特徴とする、請求項1に記載の製法。
- 前記電気伝導性接着材料を前記ダイの裏側に前塗布することを特徴とする、請求項16に記載の製法。
- 前記ダイの取付に先立って前記電気伝導性接着材料を前記ダイパッドに塗布することを特徴とする、請求項16に記載の製法。
- 前記電気伝導性接着材料の延展がオキサイド防止帯によって抑えられることを特徴とする、請求項16に記載の製法。
- 電気伝導性のクリップを前記ダイ上の接触点とピンとの間に設ける工程をさらに含むことを特徴とする、請求項16に記載の製法。
- 前記パンチング加工によって周囲の金属ロールの直交する部分およびダイパッドと一体になった少なくとも2つのピンを作ることを特徴とする、請求項1に記載の製法。
- 裏側にスタンピング加工による窪みを有するダイパッドと、
前記ダイパッドによって支持されるダイと、
結合構造体を通して前記ダイと電気的連絡をなすように形状を決められた複数のピンと、
前記ダイと前記結合構造体および、前記ピンとスタンピング加工された窪みの少なくとも一部を封入しているプラスチックパッケージボディと、
を具備する半導体素子パッケージ。 - 前記ダイパッドの厚さが約4−20ミル、前記複数のピンの幅が最小約0.15mm、間隔幅が最小約0.4mmであることを特徴とする、請求項22に記載の半導体素子パッケージ。
- ダイパッドと、
前記ダイパッドによって支持されるダイと、
結合構造体を通して前記ダイと電気的連絡をなすように形状を決められたピンであって、スタンピング加工によって形成された持ち上げられた部分を有する前記ダイパッドに隣接するピンと、
前記ダイと前記結合構造体および、前記ピンの持ち上げられた部分と前記ダイパッドの少なくとも一部を封入しているプラスチックパッケージボディと、
を具備する半導体素子パッケージ。 - 前記持ち上げられた部分の高さが前記ダイの厚さと一致することを特徴とする、請求項24に記載の半導体素子パッケージ。
- 前記ダイパッドの厚さが約4−20ミル、複数のピンの幅が最小0.15mm、間隔幅が最小約0.4mmであることを特徴とする、請求項24に記載の半導体素子パッケージ。
- ダイパッドと、
前記ダイパッドによって支持されるダイと、
結合構造体を通して前記ダイと電気的連絡をなすように形状を決められたピンであって、スタンピング加工によって形成された複雑な横断面外形を持つ部分を有するピンと、
前記ダイと前記結合構造体および、前記ピンの複雑な横断面外形と前記ダイパッドの少なくとも一部を封入しているプラスチックパッケージボディと、
を具備する半導体素子パッケージ。 - 前記ダイパッドの厚さが約4−20ミル、複数のピンの幅が最小約0.15mm、間隔幅が最小約0.4mmであることを特徴とする、請求項27に記載の半導体素子パッケージ。
- 前記複雑な横断面外形が、面取り型、凹型、凸型、砂時計型、T字型、I字型、もしくは鋸歯型から選択される、請求項27に記載の半導体素子パッケージ。
- ダイパッドと、
前記ダイパッドによって支持されるダイと、
結合構造体を通して前記ダイと電気的連絡をなすように形状を決められたピンであって、前記ダイパッドに隣接する部分にスタンピング加工によって形成された窪みを有するピンと、
前記ダイと前記結合構造体および、前記ピンの持ち上げられた部分と前記ダイパッドの少なくとも一部を封入しているプラスチックパッケージボディと、
を具備する半導体素子パッケージ。 - 前記ダイパッドの厚さが約4−20ミル、複数のピンの幅が最小約0.15mm、間隔幅が最小約0.4mmであることを特徴とする、請求項30に記載の半導体素子パッケージ。
- リードフレームであって、
ダイパッドと、
ダイパッドと一体になった1番目のピンと、
ダイパッドと一体ではなく、スタンピング加工による隆起した形状を具備する2番目のピンと、を具備するリードフレームと、
前記ダイパッドの上に支持されたダイと、
第1端がダイと第2端が前記2番目のピンと電気的接触を有する結合ワイヤと、
前記ダイと前記結合ワイヤ、前記隆起した形状を封入するプラスチックパッケージボディと、
を具備する半導体素子パッケージ。 - 前記2番目のピンの一部がスタンピング加工によって作られた複雑な横断面外形を示すことを特徴とする、請求項32に記載の半導体素子パッケージ。
- シンギュレーションに先立って前記ダイパッドを安定させるために形状を決められた少なくとも2つの一体化したピンを前記ダイパッドが具備することを特徴とする、タイバー構造を持たない、請求項32に記載の半導体素子パッケージ。
- 前記隆起した形状の高さが前記ダイの厚さと一致することを特徴とする、請求項32に記載の半導体素子パッケージ。
- タイバー構造の使用を避けるように、シンギュレーション工程に先立ってダイパッドを安定させるために、周囲のフレームと一体になった少なくとも2つの一体化したピンを持つダイパッドを設ける工程を含むパッケージ製造法。
- ダイパッドと、
前記ダイパッドによって支持されるダイと、
前記ダイパッドの穴と縁の間に位置するダウンボンド・ランウェイ領域を画定するために前記ダイパッドの外周にスタンピング加工によって形成された穴と、
第1端が前記ダイの接触点と電気的連絡を有し、第2端が前記ダウンボンド・ランウェイ領域と電気的連絡を有する結合ワイヤと、
を具備する半導体素子パッケージ。
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