CN116613132A - 射频类的芯片封装结构及方法 - Google Patents
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Abstract
本发明涉及半导体封装技术领域,特指一种射频类的芯片封装结构及方法,该封装结构包括:内部形成有基岛的框架,侧部设有引脚,且引脚和基岛相对的侧面形成有一斜面和一竖向面,斜面与对应的竖向面间的夹角大于90°;芯片,其上设有铜柱,通过铜柱与基岛和引脚连接;设于基岛和引脚之上并包覆芯片的塑封结构,塑封结构还设于基岛和引脚之间。本发明的封装结构在框架的基岛和引脚的侧面形成斜面和竖向面,且斜面和竖向面间的夹角大于90°,以提升塑封时塑封料流动的稳定性并改善气泡空洞的问题。芯片通过铜柱与基岛和引脚连接,该铜柱采用Bump工艺制成,利用铜柱代替金线能够解决线材弧度不良和成本高的问题。
Description
技术领域
本发明涉及半导体封装技术领域,特指一种射频类的芯片封装结构及方法。
背景技术
在半导体封装领域,射频类的产品采用打线(wire bonding)的方式实现芯片与框架引脚连接,如图1所示,芯片12通过DAF胶层15粘贴在框架11上,芯片12和框架11的引脚之间通过焊线14连接,塑封结构13包裹芯片12并将框架11上空隙填满。该射频类的产品对焊线14的弧度要求极为严格,打线形成的焊线14的弧度必须满足在一定的范围内,该焊线14的弧度过高或过低都会在测试时产生杂音而影响产品的质量。而在量产过程中,多台设备误差很容易出现焊线弧度不良的问题。另外,为了降噪需求,焊线的线材选用金线,这样使得制作成本较高。还有框架11的底部半蚀刻后形成了阴角,该阴角处易出现气泡排不出而使得塑封结构13在该阴角处形成空洞。
发明内容
本发明的目的在于克服现有技术的缺陷,提供一种射频类的芯片封装结构及方法,解决现有的射频类产品采用打线方式连接存在的易出现焊线弧度不良的问题、金线成本较高的问题以及塑封结构易形成空洞等的问题。
实现上述目的的技术方案是:
本发明提供了一种射频类的芯片封装结构,包括:
内部形成有基岛的框架,所述框架的侧部设有引脚,且所述引脚和所述基岛相对的侧面形成有一斜面和一竖向面,所述斜面与所述引脚和所述基岛的顶面连接,且所述斜面与对应的竖向面间的夹角大于90°;
芯片,其上设有铜柱,所述芯片通过所述铜柱与所述基岛和所述引脚连接;
设于所述基岛和所述引脚之上并包覆所述芯片的塑封结构,所述塑封结构还设于所述基岛和所述引脚之间。
本发明的封装结构在框架的基岛和引脚的侧面形成斜面和竖向面,且斜面和竖向面间的夹角大于90°,以提升塑封时塑封料流动的稳定性并改善气泡空洞的问题。芯片通过铜柱与基岛和引脚连接,该铜柱采用Bump工艺制成,利用铜柱代替金线能够解决线材弧度不良和成本高的问题,且铜柱在测试时不会产生噪音等问题,能够提升产品的质量,且可靠性高。
本发明射频类的芯片封装结构的进一步改进在于,所述基岛和所述引脚的顶面对应所述芯片上的铜柱设有定位槽。
本发明射频类的芯片封装结构的进一步改进在于,所述芯片内设有重布线层,所述重布线层与所述铜柱连接。
本发明射频类的芯片封装结构的进一步改进在于,所述基岛和所述引脚的竖向面的高度大于形成所述塑封结构的塑封颗粒的粒径。
本发明射频类的芯片封装结构的进一步改进在于,所述框架上设有镍钯金涂层。
本发明射频类的芯片封装结构的进一步改进在于,所述斜面与所述竖向面间的夹角为135°。
本发明还提供了一种射频类的芯片封装方法,包括如下步骤:
提供晶圆,对所提供的晶圆采用凸点工艺在晶圆的端口处形成铜柱;
对所述晶圆进行背面研磨;
对所述晶圆进行切割以形成多个芯片,所形成的芯片上设有铜柱;
提供框架,所提供的框架上设有基岛和引脚,且所述基岛和引脚相对的侧面形成有一斜面和一竖向面,所述斜面与所述引脚和所述基岛的顶面连接,且所述斜面与对应的竖向面间的夹角大于90°;
将芯片采用倒装芯片工艺贴在所述框架上对应的基岛和引脚上;
对所述框架进行烘烤和清洗;
对所述框架进行塑封以形成包覆所述芯片的塑封结构,所述塑封结构位于对应的基岛和引脚之上,还位于对应的基岛和引脚之间;
对所述框架进行条状切割以形成射频类的芯片封装体。
本发明射频类的芯片封装方法的进一步改进在于,提供框架时,于所提供的框架的引脚和基岛的顶面对应所述芯片上的铜柱施作定位槽。
本发明射频类的芯片封装方法的进一步改进在于,提供框架时,对所提供的框架的底部进行半蚀刻,半蚀刻的深度大于形成所述塑封结构的塑封颗粒的粒径。
本发明射频类的芯片封装方法的进一步改进在于,所述框架上涂覆有镍钯金涂层。
附图说明
图1为现有打线方式的芯片封装结构。
图2为本发明射频类的芯片封装结构的剖视图。
图3为图2中A处的局部放大示意图。
附图标记说明:11-框架,12-芯片,13-塑封结构,14-焊线,15-DAF胶层;21-框架,211-基岛,212-引脚,213-斜面,214-竖向面,215-定位槽,22-芯片,221-铜柱,23-塑封结构,24-粘结层。
具体实施方式
下面结合附图和具体实施例对本发明作进一步说明。
参阅图2,本发明提供了一种射频类的芯片封装结构及方法,用于解决传统封装使用金线焊接易出现弧度不良,焊球脱落等问题且成本高,而使用铜材质的线材易出现上板测试产生噪音的问题。传统封装采用DAF胶粘贴芯片,在塑封时,塑封料高温会让芯片背部的胶分层,进而出现芯片粘贴不牢固,可靠性验证时芯片位置发生变动、脱落等问题。框架底部半蚀刻区域形成90°的阴角,塑封时易出现气泡排不出而形成空洞的问题。本发明的射频类的芯片封装结构能够解决上述问题,具有高可靠性和稳定性,寿命长,能够满足市场上手机和蓝牙等消费类电子产品领域的需求。下面结合附图对本发明射频类的芯片封装结构及方法进行说明。
参阅图2,显示了本发明射频类的芯片封装结构的剖视图。参阅图3,显示了图2中A处的局部放大示意图。下面结合图2和图3,对本发明射频类的芯片封装结构进行说明。
如图2和图3所示,本发明的射频类的芯片封装结构包括框架21、芯片22以及塑封结构23,框架21内部形成有基岛211,侧部形成有引脚212,引脚212和基岛211相对的侧面形成有一斜面213和一竖向面214,斜面213与引脚212和基岛211的顶面连接,且斜面213与对应的竖向面214间的夹角大于90°;芯片22上设有铜柱221,芯片22通过铜柱221与基岛211和引脚212连接;塑封结构23设于基岛211和引脚212上并包覆芯片22,该塑封结构23还设于基岛211和引脚212之间。
本发明的框架21的基岛211和引脚212的侧面通过形成斜面213和竖向面214,且该斜面和竖向面间形成夹角大于90°,相对于现有技术中图1所示的呈90°的阴角,本发明的斜面和竖向面能够提升塑封时塑封料流动的稳定性并改善气泡空洞的问题。
芯片22通过铜柱221与基岛211和引脚212连接,该铜柱221采用Bump工艺制成,利用铜柱221代替金线能够解决线材弧度不良和成本高的问题,且铜柱221在测试时不会产生噪音等问题,能够提升产品的质量和可靠性。
在本发明的一种具体实施方式中,如图2和图3所示,基岛211和引脚212的顶面对应芯片22上的铜柱221设有定位槽215,该定位槽215的尺寸大于铜柱221的尺寸。通过设置定位槽215定位铜柱221的安装位置,能够提升芯片粘贴的精度和牢固性。
芯片22上的铜柱221的底部通过粘结层24粘贴固定在定位槽215内。
粘结层24较佳为焊锡层。具体地,芯片22的粘贴采用倒装工艺,利用第一吸嘴吸取芯片的正面,接着翻转180°,第二吸嘴吸取芯片的背面,移动到指定位置,蘸取助焊剂和锡膏,然后将芯片22上的铜柱粘贴在框架21上指定的位置进行固定。
芯片采用倒装,相比于传统封装在尺寸和厚度上能够缩小20%左右。定位槽的设置,便于铜柱蘸上锡膏和助焊剂后的精确定位,且不会出现锡膏污染的现象。
在本发明的一种具体实施方式中,如图2所示,芯片22内设有重布线层,该重布线层与铜柱221连接。
对芯片内部电路重新布局并引出铜柱221,用铜柱221代替传统的金线或铜线,解决了线材的弧度不良,球脱,成本高,可靠性测试存在噪音等的问题。
在本发明的一种具体实施方式中,如图2所示,基岛211和引脚212的竖向面214的高度大于形成塑封结构23的塑封颗粒的粒径。
形成塑封结构23的塑封料使用CEL-9240HF10TR-Q(53C) 16X6.8g,该塑封料的塑封颗粒的粒径在53um左右,竖向面214的高度在65um左右。
进一步地,斜面213与竖向面214间的夹角为135°。如此能够提高塑封过程中模流的稳定性,改善气泡空洞的问题。
在本发明的一种具体实施方式中,框架21上设有镍钯金涂层。通过设置镍钯金涂层,能够改善芯片封装后在电镀镀锡长晶须问题且耐酸碱腐蚀提升,可提高终端产品的使用寿命。
在本发明的一种具体实施方式中,框架21上形成有多个方框单元,每一方框单元对应形成一个封装结构,该框架21由横纵向交错设置的多个框条形成,在每一个方框单元的框条内侧设有对应的基岛和引脚,在每一个方框单元内设置芯片和塑封结构,在条状切割后就能够得到多个封装体了,也即射频类的产品。
本发明还提供了一种射频类的芯片封装方法,下面对该封装方法进行说明。
本发明的封装方法包括如下步骤:
提供晶圆,对所提供的晶圆采用凸点工艺在晶圆的端口处形成铜柱;
对晶圆进行背面研磨;
结合图2所示,对晶圆进行切割以形成多个芯片,所形成的芯片22上设有铜柱221;
提供框架,所提供的框架21上设有基岛211和引脚212,且基岛211和引脚212相对的侧面包括一斜面213和一竖向面214,斜面213与引脚212和基岛211的顶面连接,且斜面213与对应的竖向面214间的夹角大于90°;
将芯片22采用倒装芯片工艺贴在框架21上对应的基岛211和引脚212上;
对框架进行烘烤和清洗;
对框架进行塑封以形成包覆芯片的塑封结构23,塑封结构位于对应的基岛和引脚之上,还位于对应的基岛和引脚之间;
对框架进行条状切割以形成射频类的芯片封装体。
在本发明的一种具体实施方式中,提供框架时,于所提供的框架的引脚和基岛的顶面对应芯片上的铜柱施作定位槽。结合图3所示,定位槽215的尺寸大于铜柱221的尺寸。通过设置定位槽215定位铜柱221的安装位置,能够提升芯片粘贴的精度和牢固性。
在本发明的一种具体实施方式中,提供框架时,对所提供的框架的底部进行半蚀刻,半蚀刻的深度大于形成塑封结构的塑封颗粒的粒径。
在本发明的一种具体实施方式中,框架上涂覆有镍钯金涂层。
对晶圆采用凸点工艺在晶圆的端口处形成铜柱的步骤包括:
金属沉积步骤是UBM(凸点下金属化层)的沉积和凸点本身的沉积,而UBM的沉积通常采用Sputter(溅射),Electroless(化学镀),Plating(电镀)方式实现;凸点本身的沉积通常采用电镀,植球,印刷的方式实现。当晶圆上的I/O排布受限时,通常会通过RDL(重布线层)对晶圆上的I/O位置进行重新布局,使新的位置满足对焊料球最小间距的要求,并使新韩区按照阵列排布,即满足Bumping工艺基本要求。常见的RDL材料是电镀铜(Plated Cu)辅以打底的钛、铜溅射层;铜层表面再按需要覆盖相应的保护层油墨。
本发明的封装方法的流程包括晶圆接收;Bumping;背面研磨;晶圆贴片;正面揭膜;晶圆切割;倒装芯片;烘烤;清洗;塑封;烘烤;印字;条状切割;测试。
传统的封装流程包括晶圆接收;正面贴膜;背面研磨;晶圆贴片;正面揭膜;晶圆切割;芯片粘贴;烘烤;等离子清洗;焊线;塑封;烘烤;电镀;印字;条状切割;测试。
本发明的封装流程相比于传统的封装流程能够节省等离子清洗、焊线、电镀等工艺步骤,简化了封装过程,提高封装效率。
以上结合附图实施例对本发明进行了详细说明,本领域中普通技术人员可根据上述说明对本发明做出种种变化例。因而,实施例中的某些细节不应构成对本发明的限定,本发明将以所附权利要求书界定的范围作为本发明的保护范围。
Claims (10)
1.一种射频类的芯片封装结构,其特征在于,包括:
内部形成有基岛的框架,所述框架的侧部设有引脚,且所述引脚和所述基岛相对的侧面形成有一斜面和一竖向面,所述斜面与所述引脚和所述基岛的顶面连接,且所述斜面与对应的竖向面间的夹角大于90°;
芯片,其上设有铜柱,所述芯片通过所述铜柱与所述基岛和所述引脚连接;
设于所述基岛和所述引脚之上并包覆所述芯片的塑封结构,所述塑封结构还设于所述基岛和所述引脚之间。
2.如权利要求1所述的射频类的芯片封装结构,其特征在于,所述基岛和所述引脚的顶面对应所述芯片上的铜柱设有定位槽。
3.如权利要求1所述的射频类的芯片封装结构,其特征在于,所述芯片内设有重布线层,所述重布线层与所述铜柱连接。
4.如权利要求1所述的射频类的芯片封装结构,其特征在于,所述基岛和所述引脚的竖向面的高度大于形成所述塑封结构的塑封颗粒的粒径。
5.如权利要求1所述的射频类的芯片封装结构,其特征在于,所述框架上设有镍钯金涂层。
6.如权利要求1所述的射频类的芯片封装结构,其特征在于,所述斜面与所述竖向面间的夹角为135°。
7.一种射频类的芯片封装方法,其特征在于,包括如下步骤:
提供晶圆,对所提供的晶圆采用凸点工艺在晶圆的端口处形成铜柱;
对所述晶圆进行背面研磨;
对所述晶圆进行切割以形成多个芯片,所形成的芯片上设有铜柱;
提供框架,所提供的框架上设有基岛和引脚,且所述基岛和引脚相对的侧面形成有一斜面和一竖向面,所述斜面与所述引脚和所述基岛的顶面连接,且所述斜面与对应的竖向面间的夹角大于90°;
将芯片采用倒装芯片工艺贴在所述框架上对应的基岛和引脚上;
对所述框架进行烘烤和清洗;
对所述框架进行塑封以形成包覆所述芯片的塑封结构,所述塑封结构位于对应的基岛和引脚之上,还位于对应的基岛和引脚之间;
对所述框架进行条状切割以形成射频类的芯片封装体。
8.如权利要求7所述的射频类的芯片封装方法,其特征在于,提供框架时,于所提供的框架的引脚和基岛的顶面对应所述芯片上的铜柱施作定位槽。
9.如权利要求7所述的射频类的芯片封装方法,其特征在于,提供框架时,对所提供的框架的底部进行半蚀刻,半蚀刻的深度大于形成所述塑封结构的塑封颗粒的粒径。
10.如权利要求7所述的射频类的芯片封装方法,其特征在于,所述框架上涂覆有镍钯金涂层。
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