JP2009158738A - 半導体装置と半導体記憶装置 - Google Patents
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Abstract
【解決手段】配線基板上2には第1の素子群12を構成する複数の半導体素子9A〜9Dがパッド配列辺を同方向に向けて階段状に積層されている。第1の素子群12上には第2の素子群13を構成する複数の半導体素子9E〜9Hが第1の素子群11とパッド配列辺を同方向に向けて階段状に積層されている。第2の素子群13は第1の素子群12に対して電極パッド11の配列方向にずらした状態で配置されている。各半導体素子9は金属ワイヤ14を介して配線基板2の接続パッド7と電気的に接続されている。
【選択図】図1
Description
Claims (5)
- 素子搭載部と接続パッドとを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1の素子群と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記第1の素子群上に前記第1の素子群とパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第2の素子群と、
前記第1および第2の素子群を構成する前記複数の半導体素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する金属ワイヤと、
前記第1および第2の素子群を前記金属ワイヤと共に封止するように、前記配線基板上に形成された封止樹脂層とを具備し、
前記第2の素子群は前記第1の素子群に対して前記電極パッドの配列方向にずらした状態で配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2の素子群はそれを構成する前記複数の半導体素子の前記電極パッドが前記第1の素子群を構成する前記複数の半導体素子の前記電極パッドの間に位置するように配置されていることを特徴とする半導体装置。 - 外部接続端子を備える第1の主面と、素子搭載部と接続パッドとを備え、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1のメモリ素子群と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記第1のメモリ素子群上に前記第1のメモリ素子群とパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第2のメモリ素子群と、
前記第2のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、
前記第1および第2のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記第1および第2のメモリ素子群と前記コントローラ素子を前記第1および第2の金属ワイヤと共に封止するように、前記配線基板の前記第2の主面上に形成された封止樹脂層とを具備し、
前記第2のメモリ素子群は前記第1のメモリ素子群に対して前記電極パッドの配列方向にずらした状態で配置されていることを特徴とする半導体記憶装置。 - 請求項3記載の半導体記憶装置において、
前記第2のメモリ素子群はそれを構成する前記複数のメモリ素子の前記電極パッドが前記第1のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドの間に位置するように配置されていることを特徴とする半導体記憶装置。 - 請求項3または請求項4記載の半導体記憶装置において、
前記第1の金属ワイヤは、前記第1および第2のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続するデータ信号用金属ワイヤと、前記第1のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第1の制御信号用金属ワイヤと、前記第2のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第2の制御信号用金属ワイヤとを備え、前記第2の制御信号用金属ワイヤは前記第1のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッド間にワイヤリングされていることを特徴とする半導体記憶装置。
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JP2007335665A JP5150242B2 (ja) | 2007-12-27 | 2007-12-27 | 半導体記憶装置 |
US12/343,921 US8004071B2 (en) | 2007-12-27 | 2008-12-24 | Semiconductor memory device |
US13/172,571 US8395268B2 (en) | 2007-12-27 | 2011-06-29 | Semiconductor memory device |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011187914A (ja) * | 2009-08-13 | 2011-09-22 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2011211149A (ja) * | 2009-08-13 | 2011-10-20 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2011211150A (ja) * | 2009-08-13 | 2011-10-20 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2013522887A (ja) * | 2010-03-18 | 2013-06-13 | モサイド・テクノロジーズ・インコーポレーテッド | オフセットダイスタッキングを用いたマルチチップパッケージおよびその作成方法 |
JP2014513870A (ja) * | 2011-05-18 | 2014-06-05 | サンディスク セミコンダクター (シャンハイ) カンパニー, リミテッド | ウォータフォール・ワイヤボンディング |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2001217383A (ja) * | 2000-01-31 | 2001-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2001298150A (ja) * | 2000-04-14 | 2001-10-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006313798A (ja) * | 2005-05-06 | 2006-11-16 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007227537A (ja) * | 2006-02-22 | 2007-09-06 | Renesas Technology Corp | 不揮発性記憶装置 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001217383A (ja) * | 2000-01-31 | 2001-08-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2001298150A (ja) * | 2000-04-14 | 2001-10-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006313798A (ja) * | 2005-05-06 | 2006-11-16 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007227537A (ja) * | 2006-02-22 | 2007-09-06 | Renesas Technology Corp | 不揮発性記憶装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011187914A (ja) * | 2009-08-13 | 2011-09-22 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2011211149A (ja) * | 2009-08-13 | 2011-10-20 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2011211150A (ja) * | 2009-08-13 | 2011-10-20 | Sk Link:Kk | 半導体装置及びその製造方法 |
JP2013522887A (ja) * | 2010-03-18 | 2013-06-13 | モサイド・テクノロジーズ・インコーポレーテッド | オフセットダイスタッキングを用いたマルチチップパッケージおよびその作成方法 |
US9177863B2 (en) | 2010-03-18 | 2015-11-03 | Conversant Intellectual Property Management Inc. | Multi-chip package with offset die stacking and method of making same |
JP2014513870A (ja) * | 2011-05-18 | 2014-06-05 | サンディスク セミコンダクター (シャンハイ) カンパニー, リミテッド | ウォータフォール・ワイヤボンディング |
US9704797B2 (en) | 2011-05-18 | 2017-07-11 | Sandisk Information Technology (Shanghai) Co., Ltd. | Waterfall wire bonding |
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