JP2009099840A - 半導体基板、及び半導体装置の製造方法 - Google Patents
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Abstract
【解決手段】複数の半導体チップが実装された実装領域2の外周部の枠部3に配置され認識カメラによって位置を巨視的に検出するための第1の認識マーク11と、第1の認識マーク11よりも小さく形成され認識カメラによって位置を微視的に検出するための第2の認識マーク12と、を備える。第2の認識マーク12は、中心線がダイシングライン4の延長線上に配置され、中心線に対して線対称に形成されたパターン形状を有している。このパターン形状は、ダイシングライン4に平行な方向に占める比率が、ダイシングライン4に垂直な方向に占める比率よりも大きく形成され、パターン形状を形成するためのエッチング液の流動を促す流動領域13を含んでいる。
【選択図】図1
Description
複数の半導体素子が実装された実装領域の外周部の枠部に配置され検出手段によって位置を巨視的に検出するための第1の認識マークと、第1の認識マークよりも小さく形成され検出手段によって位置を微視的に検出するための第2の認識マークと、を備える。そして、第2の認識マークは、中心線が分割線の延長線上に配置され、中心線に対して線対称に形成されたパターン形状を有している。パターン形状は、分割線に平行な方向に占める比率が、分割線に垂直な方向に占める比率よりも大きく形成され、このパターン形状を形成するためのエッチング液の流動を促す流動領域を含んでいる。
複数の半導体素子が実装された実装領域の外周部の枠部に配置され検出手段によって位置を巨視的に検出するための第1の認識マークと、第1の認識マークよりも小さく形成され検出手段によって位置を微視的に検出するための第2の認識マークと、を備える。そして、第2の認識マークは、中心線が分割線の延長線上に配置され、中心線に対して線対称に形成されたパターン形状を有し、このパターン形状が、複数の単純図形を組み合わせて構成されている。
認識カメラによって第1の認識マークを認識することによって半導体基板の位置を検出する第1工程と、認識カメラの倍率を高くして第2の認識マークを認識することによって半導体基板の分割線の位置を検出する第2工程と、半導体基板を分割線に沿って切断する第3工程と、を有する。
上述した実施形態では、第2の認識マーク12として楕円形をなすパターン形状に形成されたが、エッチング液が均一に流れてダレが生じるのが抑えられる形状であれば、楕円形状以外の他の形状であっても良い。エッチング液が均一に流れる形状の他の例としては、例えば図6(a)に示すような形状が挙げられる。
2 実装領域
3 枠部
4 ダイシングライン(分割線)
8 半導体チップ
11 第1の認識マーク
12 第2の認識マーク
13 流動領域
16 半導体パッケージ
Claims (6)
- 複数の半導体素子がマトリックス状に配列されて実装され、実装された前記複数の半導体素子ごとに個々に切断して分離するための分割線を備える半導体基板であって、
前記複数の半導体素子が実装された実装領域の外周部の枠部に配置され、検出手段によって位置を巨視的に検出するための第1の認識マークと、
前記第1の認識マークよりも小さく形成され、前記検出手段によって位置を微視的に検出するための第2の認識マークと、を備え、
前記第2の認識マークは、中心線が前記分割線の延長線上に配置され、該中心線に対して線対称に形成されたパターン形状を有し、
前記パターン形状は、前記分割線に平行な方向に占める比率が、前記分割線に垂直な方向に占める比率よりも大きく形成され、前記パターン形状を形成するためのエッチング液の流動を促す流動領域を含んでいる、ことを特徴とする半導体基板。 - 前記第2の認識マークの前記パターン形状は、前記分割線の延長線上に長軸が位置する楕円形状である、請求項1に記載の半導体基板。
- 前記第2の認識マークの前記パターン形状は、前記分割線の延長線上に配置された直線部と、該直線部を挟んで平行に配置された一対の直線部とを有している、請求項1に記載の半導体基板。
- 複数の半導体素子がマトリックス状に配列されて実装され、実装された前記複数の半導体素子ごとに個々に切断して分離するための分割線を備える半導体基板であって、
前記複数の半導体素子が実装された実装領域の外周部の枠部に配置され、検出手段によって位置を巨視的に検出するための第1の認識マークと、
前記第1の認識マークよりも小さく形成され、前記検出手段によって位置を微視的に検出するための第2の認識マークと、を備え、
前記第2の認識マークは、中心線が前記分割線の延長線上に配置され、該中心線に対して線対称に形成されたパターン形状を有し、該パターン形状が、複数の単純図形を組み合わせて構成されている、ことを特徴とする半導体基板。 - 前記第2の認識マークの前記パターン形状は、前記分割線上に位置する円形部と、該円形部を包囲する四角形状の枠部とを有している、請求項5に記載の半導体基板。
- 請求項1ないし5のいずれか1項に記載の半導体基板を用いた、半導体装置の製造方法であって、
認識カメラによって前記第1の認識マークを認識することによって前記半導体基板の位置を検出する第1工程と、
前記認識カメラの倍率を高くして前記第2の認識マークを認識することによって前記半導体基板の前記分割線の位置を検出する第2工程と、
前記半導体基板を前記分割線に沿って切断する第3工程と、
を有する、半導体装置の製造方法。
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JP2007271205A JP5466820B2 (ja) | 2007-10-18 | 2007-10-18 | 半導体基板、及び半導体装置の製造方法 |
US12/285,831 US7759808B2 (en) | 2007-10-18 | 2008-10-15 | Semiconductor substrate including first and second recognition marks and method for manufacturing semiconductor device |
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WO2006019911A1 (en) * | 2004-07-26 | 2006-02-23 | Sun Microsystems, Inc. | Multi-chip module and single-chip module for chips and proximity connectors |
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JP5466820B2 (ja) | 2014-04-09 |
US20090102071A1 (en) | 2009-04-23 |
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