JP2009053970A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009053970A JP2009053970A JP2007220507A JP2007220507A JP2009053970A JP 2009053970 A JP2009053970 A JP 2009053970A JP 2007220507 A JP2007220507 A JP 2007220507A JP 2007220507 A JP2007220507 A JP 2007220507A JP 2009053970 A JP2009053970 A JP 2009053970A
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Abstract
【解決手段】本発明の実施の形態に係る半導体装置は、複数の半導体素子と、前記複数の半導体素子を実装し、外部機器と接続する複数の端子を有する基板と、前記複数の半導体素子の実装領域外、かつ前記複数の端子のうち電源端子近傍の前記基板上に実装されたヒューズと、を具備し、前記電源端子に接続される電源供給ラインは、前記ヒューズを経由して前記複数の半導体素子に接続されている。
【選択図】図6
Description
図1及び図2に示すように、本発明の第1の実施の形態に係るメモリカード1は、基板2と、素子実装領域外5に形成された複数の基板パッド3と、基板2の凸部7に実装された複数の電子部品4(例えば、コンデンサ等)と、素子実装領域外5の電源端子3A(図6参照)近傍に実装されたヒューズ6と、素子実装領域内に実装されたメモリチップ11と、メモリチップ11の上層(図中の手前側)に積層して実装されたコントローラチップ12と、を具備する。
本発明の第2の実施の形態は、前述の第1の実施の形態に係るメモリカード1において、ヒューズの実装位置を変えた例を説明するものである。
本発明の第3の実施の形態は、前述の第1、第2の実施の形態に係るメモリカード1、20とは異なり、更に複数のメモリチップを階段状に積層したメモリカードに対してヒューズを実装する例を説明するものである。
本発明の第4の実施の形態は、前述の第3の実施の形態に係るメモリカード30とは異なり、複数のメモリチップを直上に積層したメモリカードに対してヒューズを実装する例を説明するものである。
メモリチップ11とコントローラチップ12を2段に積層して、樹脂モールド15により一体的に形成したメモリカード1の各部の概略寸法を示す。
パッケージ全体の厚み:約700μm、モールド厚:約550μm、基板2の厚み:約170μm、メモリチップ11の厚み:約150μm、コントローラチップ12の厚み:約120μm、チップ間の絶縁膜の厚み:約20μm
メモリチップ34〜37とコントローラチップ38を5段に階段状に積層して、樹脂モールド41により一体的に形成したメモリカード30の各部の概略寸法を示す。
パッケージ全体の厚み:約700μm、モールド厚:約600μm、基板31の厚み:約120μm、1段目のメモリチップ34の厚み:約80μm、1段目の絶縁膜39の厚み:20μm、2段目のメモリチップ35の厚み:約70μm、2段目の絶縁膜39の厚み:10μm、3段目のメモリチップ36の厚み:約70μm、3段目の絶縁膜39の厚み:10μm、4段目のメモリチップ36の厚み:約70μm、4段目の絶縁膜39の厚み:10μm、5段目のコントローラチップ38の厚み:約70μm
メモリチップ54、56とコントローラチップ58を3段に積層して、樹脂モールド61により一体的に形成したメモリカード50の各部の概略寸法を示す。
パッケージ全体の厚み:約700μm、モールド厚:約550μm、基板51の厚み:約170μm、1段目のメモリチップ54の厚み:約150μm、1段目の絶縁膜55の厚み:20μm、2段目のメモリチップ56の厚み:約70μm、2段目の絶縁膜57の厚み:10μm、3段目のコントローラチップ58の厚み:約70μm、3段目の絶縁膜59の厚み:約20μm
2、31、51 基板
3、33、53 基板パッド
3A 電源端子
4 電子部品
5 素子実装領域外
6 ヒューズ
6A ヒューズ端子
7、21 凸部
11、34〜37、54、56 メモリチップ
12、38、58 コントローラチップ
13、40、60 ボンディングワイヤ
15、41、61 樹脂モールド
16 電源供給ライン
Claims (5)
- 複数の半導体素子と、
前記複数の半導体素子を実装し、外部機器と接続する複数の端子を有する基板と、
前記複数の半導体素子の実装領域外、かつ前記複数の端子のうち電源端子近傍の前記基板上に実装されたヒューズと、を具備し、
前記電源端子に接続される電源供給ラインは、前記ヒューズを経由して前記複数の半導体素子に接続されたことを特徴とする半導体装置。 - 前記基板は、前記複数の半導体素子と前記複数の端子とを接続する複数のパッドを該複数の半導体素子の実装領域外の周囲に形成し、
前記ヒューズは、前記パッド形成領域内の前記電源端子近傍に実装されたことを特徴とする請求項1記載の半導体装置。 - 前記基板は、前記複数の半導体素子の実装領域外に他の素子を実装する凸部を有し、
前記ヒューズは、前記凸部に実装されたことを特徴とする請求項1記載の半導体装置。 - 前記複数の半導体素子は、前記基板上に積層して実装され、
前記複数の半導体素子、前記他の素子、前記ヒューズ、及び前記基板全体は、樹脂モールドにより封止されてカード状に一体形成されたことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。 - 前記ヒューズは、前記電源供給ラインに過電流が流れた際に溶断して、前記複数の半導体素子に対する電源供給を遮断することを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2007220507A JP2009053970A (ja) | 2007-08-28 | 2007-08-28 | 半導体装置 |
US12/199,913 US8014223B2 (en) | 2007-08-28 | 2008-08-28 | Semiconductor device |
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JP2007220507A JP2009053970A (ja) | 2007-08-28 | 2007-08-28 | 半導体装置 |
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JP2009053970A true JP2009053970A (ja) | 2009-03-12 |
JP2009053970A5 JP2009053970A5 (ja) | 2009-10-01 |
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KR20110107590A (ko) * | 2010-03-25 | 2011-10-04 | 삼성전기주식회사 | 터치패널 |
JP5996500B2 (ja) * | 2013-09-11 | 2016-09-21 | 株式会社東芝 | 半導体装置および記憶装置 |
US10121767B2 (en) * | 2015-09-10 | 2018-11-06 | Toshiba Memory Corporation | Semiconductor storage device and manufacturing method thereof |
US11514996B2 (en) * | 2017-07-30 | 2022-11-29 | Neuroblade Ltd. | Memory-based processors |
US10566276B2 (en) * | 2017-11-08 | 2020-02-18 | Texas Instruments Incorporated | Packaged semiconductor system having unidirectional connections to discrete components |
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US8014223B2 (en) | 2011-09-06 |
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