US20070228509A1 - Semiconductor device and memory card using the same - Google Patents
Semiconductor device and memory card using the same Download PDFInfo
- Publication number
- US20070228509A1 US20070228509A1 US11/691,716 US69171607A US2007228509A1 US 20070228509 A1 US20070228509 A1 US 20070228509A1 US 69171607 A US69171607 A US 69171607A US 2007228509 A1 US2007228509 A1 US 2007228509A1
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- 239000000758 substrate Substances 0.000 claims description 69
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- 238000007789 sealing Methods 0.000 claims description 23
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 15
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- 238000004519 manufacturing process Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000009413 insulation Methods 0.000 description 7
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- 238000003763 carbonization Methods 0.000 description 5
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- 238000006731 degradation reaction Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
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- 239000012790 adhesive layer Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0256—Electrical insulation details, e.g. around high voltage areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
- H05K2201/0761—Insulation resistance, e.g. of the surface of the PCB between the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Definitions
- the present invention relates to a semiconductor device and a memory card using the same.
- Semiconductor memory cards having a NAND type flash memory or the like built therein are downsized while having larger capacity.
- SDTM memory card is presented in three sizes, a size of a normal SDTM card, a size of a mini SDTM card and a size of a micro SDTM card, in which even the micro SDTM card is expected to have a larger capacity.
- the semiconductor device having a built-in semiconductor element such as a memory element, a controller element or the like forms the memory card without being accommodated in a case such as a base card.
- a circuit board frame in which regions to form a plurality of memory cards are arranged in a matrix manner, is prepared at first.
- An external connecting terminal is formed in each of the card-forming regions by electrolytic plating or the like, and after that a semiconductor element is mounted on a rear surface side.
- the semiconductor elements and the circuit boards are electrically connected and a sealing resin is formed by molding on the rear surface of the circuit board frame to seal the semiconductor elements mounted on the plurality of card-forming regions all at once.
- the circuit board frame together with the sealing resin is cut in accordance with the card forming regions to manufacture the plurality of memory cards all at once.
- a cut-out portion, a constricted portion and the like indicating a head or rear direction and an upper or lower direction of the card when the card is equipped into a card slot is provided at an outer peripheral portion of the memory card.
- the cut-out portion, the constricted portion and the like are formed at the case.
- the cut-out portion, the constricted portion and the like need to be formed at the semiconductor device itself.
- the curved portion needs to be cut at a lower speed than the speed to cut the linear portion, in which the machining efficiency downs further.
- the laser machining and the water jet machining effective for cutting the curved portion exhibits a higher cutting efficiency as compared to the water jet machining, whereas a cooling efficiency thereof downs at the time of a low-speed cutting, in which a problem of heat generation is caused at the cut portion. Affected by the heat generated at the time of the cutting, there arise problems such as an insulation performance down between the wirings, a short circuit caused by carbonized resist or core material composing the circuit board, and further an easily-caused characteristic degradation of the semiconductor element.
- a semiconductor device includes: a substrate including a first main surface, a second main surface on an opposite of the first main surfaces, and a curved portion provided in at least one side of an external shape thereof; a semiconductor element mounted on at least one of the first and second main surfaces of the substrate; and a wiring network provided on at least one of the first and second main surfaces of the substrate, wherein distance from the side including the curved portion of the substrate to the wiring network is larger than distance from at least one of the other sides of the substrate to the wiring network.
- a semiconductor device includes: a substrate including a first main surface, a second main surface on an opposite of the first main surface, and a curved portion provided in at least one side of an external shape thereof; an external connecting terminal formed on the first main surface of the substrate; a first wiring network provided in a region except a region formed the external connecting terminal on the first main surface of the substrate; a second wiring network provided on the second main surface of the substrate; and a semiconductor element mounted on the second main surface of the substrate, wherein distance from the side including the curved portion of the substrate to the first wiring network is larger than distance from at least one of the other sides of the substrate to the first wiring network, and distance from the side including the curved portion of the substrate to the second wiring network is larger than distance from at least one of the other sides of the substrate to the second wiring network.
- a memory card includes: a substrate including a first main surface, a second main surface on an opposite of the first main surface, and a curved portion provided in at least one side of an external shape thereof; an external connecting terminal formed on the first main surface of the substrate; a first wiring network provided in a region except a region formed the external connecting terminal on the first main surface of the substrate; an insulating layer formed on the first main surface of the substrate to cover the first wiring network; a second wiring network provided on the second main surface of the substrate; a semiconductor memory element mounted on the second main surface of the substrate; and a sealing resin layer formed on the second main surface of the substrate to seal the semiconductor memory element, wherein distance from the side including the curved portion of the substrate to the first wiring network is larger than distance from at least one of the other sides of the substrate to the first wiring network, and distance from the side including the curved portion of the substrate to the second wiring network is larger than distance from at least one of the other sides of the substrate to the second wiring network.
- FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1 .
- FIG. 3 is a rear view showing the semiconductor device shown in FIG. 1 .
- FIG. 4 is a view showing an example of a second wiring network provided on a second main surface of a circuit board composing the semiconductor device shown in FIG. 1 .
- FIG. 5 is a view showing another example of the second wiring network provided on the second main surface of the circuit board composing the semiconductor device shown in FIG. 1 .
- FIG. 6 is a view showing another example of the circuit board composing the semiconductor device shown in FIG. 1 .
- FIGS. 7A , 7 B and 7 C are views showing a manufacturing process of the semiconductor device shown in FIG. 1 .
- FIGS. 8A and 8B are plan views showing a cutting step of a circuit board frame in the manufacturing process of the semiconductor device shown in FIG. 1 .
- FIGS. 9A and 9B are plan views showing another cutting step of the circuit board frame in the manufacturing process of the semiconductor device shown in FIG. 1 .
- FIG. 1 , FIG. 2 and FIG. 3 are views showing a structure of a semiconductor device according to an embodiment of the present invention, in which FIG. 1 is a sectional view of the semiconductor device, FIG. 2 is a plan view (upper view) thereof and FIG. 3 is a rear view thereof.
- a semiconductor device 1 shown in these view is composed of a memory card, and the semiconductor device 1 is used by itself as, for example, a micro SDTM standard memory card (microSDTM card).
- the semiconductor device 1 includes a circuit board 2 serving as a terminal forming substrate and an element mounting substrate.
- the circuit board 2 is formed, for example, by providing a wiring network inside or on a surface of an insulating resin substrate, and specifically, a print circuit board using glass epoxy resin, BT resin (Bsmaleimide-Triazine resin) or the like is applicable.
- the circuit board 2 includes a first main surface 2 a to be a terminal forming surface and a second main surface 2 b to be an element mounting surface.
- the circuit board 2 has substantially a rectangular shape in appearance.
- a short side 3 A corresponds to a head portion when inserting the memory card into a card slot.
- Another short side 3 B corresponds to a rear portion of the memory card.
- a long side 4 A of the circuit board 2 is provided with a cut-out portion 5 and a constricted portion 6 indicating the head, rear, upper and lower direction of the memory card.
- the cut-out portion 5 is formed by cutting out the corner portion between the short side 3 A and the long side 4 A and a part of the long side 4 A continued therefrom to make the short side 3 A be smaller than the short side 3 B.
- the constricted portion 6 is formed by cutting out a part of the long side 4 A into substantially a trapezoidal shape.
- the cut-out portion 5 and the constricted portion 6 have a complicated shape including a curved portion, respectively, and thereby shape the circuit board 2 into a complicated shape in appearance as well.
- the long side 4 A of the circuit board 2 includes the cut-out portion 5 and the constricted portion 6 having a curved portion as a part of their shapes, respectively. Further, respective corner portions 7 of the circuit board 2 are designed to be curved (have an R shape). Although, here, the cut-out portion 5 and the constricted portion 6 are described separately, these portions may be collectively referred to as a portion formed by cutting out a part of the side composing the external form of the circuit board 2 .
- the semiconductor device 1 is effective when using the circuit board 2 including the cut-out portion as described above. Further, the semiconductor device 1 is effective when using the circuit board 2 including the curved corner portion 7 .
- the first main surface 2 a of the circuit board 2 has thereon an external connecting terminal 8 to be an input/output terminal of the memory card. Further, the first main surface 2 a of the circuit board 2 includes a first wiring network 9 in the region other than the region where the external connecting terminal 8 is formed.
- the first wiring network 9 is covered by an insulating layer 10 using an insulating adhesive seal or insulating adhesive tape, and is insulated thereby.
- the first wiring network 9 is formed to have a longer distance L 11 from the long side 4 A with the cut-out portion 5 and the constricted portion 6 than distance from at least one of the other sides.
- the first wiring network 9 is formed so that the distance L 11 from the long side 4 A with the cut-out portion 5 and the constricted portion 6 to the first wiring network 9 becomes larger than a distance L 12 from the short side 3 B to the first wiring network 9 and a distance L 13 from a long side 4 B to the first wiring network 9 (L 11 >L 12 , L 11 >L 13 ).
- the distances compared with the distance L 11 from the long side 4 A are the distances L 12 , L 13 from the short side 3 B and the long side 4 B, respectively, to which the first wiring network 9 is close, and the distance from the short side 3 A through the region formed the external connecting terminal 8 is excluded.
- the distance L 11 from the long side 4 A is larger than the distance from each of the other sides except the side through the formation region of the external connecting terminal 8 .
- the first wiring network 9 has larger distances from the R-shaped corner portions 7 of the circuit board 2 than the distances (L 12 and L 13 ) from the other sides 3 B, 4 B.
- the first wiring network 9 is formed so that the distance L 11 from the long side 4 A with the cut-out portion 5 and the constricted portion 6 and the distances from the curved corner portions (corners having a R shape) 7 of the circuit board 2 become larger than the distances (L 12 , L 13 ) from the other sides 3 B, 4 B.
- FIG. 4 shows a configuration example of the second wiring network 11 .
- the second wiring network 11 is formed so that a distance L 21 from the long side 4 A with the cut-out portion 5 and the constricted portion 6 becomes larger than the distances from the other sides, namely the short side 3 A, the short side 3 B, and the long side 4 B.
- the second wiring network 11 includes plating lead wires 12 to form the external connecting terminal 8 and the like by electrolytic plating.
- the plating lead wires 12 are drawn out toward the sides except the long side 4 A with the cut-out portion 5 and the constricted portion 6 , for example, toward the short side 3 B and the long side 4 B.
- the plating lead wires 12 are drawn out to the short side 3 B and the long side 4 B, proving that the distances from the short side 3 B and the long side 4 B to the second wiring network 11 are 0 (zero).
- the second wiring network 11 is formed so that the distance L 21 from the long side 4 A becomes larger than the distance from the short side 3 A, further the distances (virtually 0 (zero)) from the short side 3 B and the long side 4 B.
- the second wiring network 11 has larger distances from the R-shaped corner portions 7 of the circuit board 2 than the distance (for example, L 22 ) from the other side.
- the second wiring network 11 is formed so that the distance L 21 from the long side 4 A with the cut-out portion 5 and the constricted portion 6 as well as the distances from the curved corner portions (corners having a R shape) 7 of the circuit board 2 become larger than the distance from each of the other sides 3 A, 3 B and 4 B.
- the second wiring network 11 is drawn out to the short side 3 B and the long side 4 B. Meanwhile, a region having no wiring formed (non-wiring region X) is provided between the long side 4 A with the cut-out portion 5 and the constricted portion 6 and the second wiring network 11 .
- the non-wiring region X is also provided between the curved-corner portions 7 and the second wiring network 11 , respectively. As will be described later, the non-wiring regions X are provided in a corresponding manner to the portions of which external shapes are processed by adopting a laser beam machining.
- the non-wiring regions X are set between the second wiring network 11 and the portions (the long side 4 A and the respective corner portions 7 ) of the circuit board 2 , of which external shapes are processed by employing the laser beam machining. This is equally applied to the first wiring network 9 .
- the portions existing in the vicinity of the short side 3 B and the long side 4 B may be removed by etching or the like as shown in FIG. 5 , after forming the external connecting terminal 8 and the like by carrying out the electrolytic plating to the circuit board 2 .
- the plating lead wires 12 are to exist at the portions distant a predetermined distance from the respective sides (the short side 3 B, the long side 4 B and the like) composing the external shape of the circuit board 2 .
- the second wiring network 11 is formed so that the distance L 21 from the long side 4 A becomes larger than the respective distances from the short side 3 A, the short side 3 B and the long side 4 B.
- FIG. 6 shows one example of dummy wirings 20 provided on the second main surface 2 b of the circuit board 2 .
- the dummy wiring 20 is provided between the long side 4 A having the curved portions based on the cut-out portion 5 and the constricted portion 6 and the curved corner portions 7 and the second wiring network 11 , respectively.
- the dummy wirings 20 do not serve as electric wirings but to serve by protecting the second wiring network 11 against an inconvenience (carbonization of a board material and the like) caused by heat generated at the time of the laser beam machining.
- the dummy wirings 20 exist independently of the second wiring network 11 . Even when the laser beam machining is carried out to the long side 4 A and the corner portions 7 and thereby the board material of the machined portions is carbonized, the dummy wirings 20 halt the carbonization by themselves. Accordingly, the second wiring network 11 is surely prevented from being adversely affected by the carbonization of the board material.
- the dummy wirings 20 may be formed with respect to the first main surface 2 a of the circuit board 2 as well.
- the dummy wiring 20 may be arranged between various laser-beam machined portions and the wiring network, and the wiring network is prevented from the adverse affect also in that case.
- First and second semiconductor elements 13 , 14 are mounted on the second main surface 2 b of the circuit board 2 .
- the first semiconductor element 13 is a semiconductor memory element such as of a NAND-type flash memory.
- the first semiconductor memory element 13 is adhered to the second main surface 2 b of the circuit board 2 via a not-shown adhesive layer.
- the number of the first semiconductor memory element 13 to be mounted is not limited to one and two or more is also acceptable.
- the second semiconductor element 14 is, for example, a controller element.
- the controller element 14 is stacked and adhered on the semiconductor memory element 13 via a not-shown adhesive layer.
- Respective electrode pads (not-shown) of the semiconductor memory element 13 and the controller element 14 are electrically connected to a connection pad provided to the second wiring network 11 via bonding wires 15 , 16 .
- the second wiring network 11 is electrically connected to the external connecting terminal 8 and the first wiring network 9 via a not-shown internal wiring (a through hole and so on) of the circuit board 2 .
- a sealing resin layer 17 such as of epoxy resin is formed by molding. The semiconductor memory element 13 and the controller element 14 are sealed by the sealing resin layer 17 .
- the semiconductor memory element 13 and the controller element 14 mounted on the second main surface 2 b of the circuit board 2 are sealed in a unified manner by the sealing resin layer 17 to form the semiconductor device (memory card) 1 .
- the sealing resin layer 17 is formed by molding with respect to a plurality of the circuit boards 2 all at a time, as will be described later.
- the sealing resin layer 17 is cut together with the circuit board 2 .
- the cut-out portion 5 and the constricted portion 6 having the same shape as of the circuit board 2 are formed. The same is equally applied to the respective corner portions of the sealing resin layer 17 , and the same curved shape (R shape) as of the corner portions of the circuit board 2 are given thereto.
- a slant portion 18 formed by cutting parts of the sealing resin layer 17 and the circuit board 2 is provided at the head side (the short side 3 A side) of the sealing resin layer 17 with an aim to facilitate the insertion/removal of the memory card.
- the slant portion 18 is provided on the surface side (the first main surface 2 a side of the circuit board 2 ) of the memory card.
- On the rear side (the short side 3 B side) of the sealing resin layer 17 On the rear side (the short side 3 B side) of the sealing resin layer 17 , a handle portion 19 formed by partially heaping the sealing resin is provided.
- the handle portion 19 is provided on the rear surface side (the second main surface 2 b side of the circuit board 2 ) of the memory card.
- the semiconductor device 1 of the present embodiment forms a memory card (for example, a micro SDTM card) by itself without using any case accommodating the semiconductor device such as a base card.
- the semiconductor device 1 is a memory card exposing its insulating layer 10 and sealing resin layer 17 outside without using a case. Therefore, the cut-out portion 5 and the constricted portion 6 indicating the head/rear and surface/rear surface directions and the like of the memory card are provided in the semiconductor device 1 itself.
- the cut-out portion 5 and the constricted portion 6 are formed by cutting the circuit board 2 together with the sealing resin layer 17 .
- the cut-out portion 5 and the constricted portion 6 are formed partially by a curved line, making a blade dicing be difficult. Therefore, the cut-out portion 5 and the constricted portion 6 are cut by adopting, for example, a laser beam machining.
- the laser beam machining may be adopted for the machining of the entire long side 4 A with the cut-out portion 5 and the constricted portion 6 . In that case, the curved portion needs to be cut at a lower speed than that to cut the linear portion. Therefore, a cooling efficiency at the time of the laser beam machining downs, raising a concern about an effect of heat generated at the cut portion.
- the distance from the side including the curved portions such as the cut-out portion 5 and the constricted portion 6 (here, the long side 4 A) to the first and second wiring networks 9 , 11 is made larger than the distance from the other sides to the first and second wiring networks 9 , 11 .
- the effect of the heat generated at the time of the laser beam machining with respect to the first and second wiring networks 9 , 11 and the semiconductor elements 13 , 14 can be prevented.
- the insulation performance down and a short circuit in the wiring networks 9 , 11 caused by the carbonization of the board material at the time of the laser beam machining, and the characteristic degradation in the semiconductor elements 13 , 14 caused by the heat generated at the time of the laser beam machining can be prevented.
- the wiring region can be ensured sufficiently in that the distances from the other sides to the wiring networks 9 , 11 are sufficiently small.
- the distances from the sides to be subject to the laser beam machining (laser-beam machined portions) to the wiring networks 9 , 11 are 0.5 mm or more.
- the non-wiring region X has a shape having a width of 0.5 mm or more.
- the distances from the long side 4 A and the corner portions 7 to the first and second wiring networks 9 , 11 are 0.5 mm or more, respectively.
- the second wiring network 11 includes the plating lead wires 12 .
- the plating lead wire 12 needs to be drawn out to the side of the circuit board 2 .
- the plating lead wires 12 are drawn out toward the sides except the long side 4 A with the cut-out portion 5 and the constricted portion 6 (the short side 3 B and the long side 4 B). Therefore, the heat generated at the time of the laser beam machining does not possibly affect the plating lead wires 12 .
- the liner short sides 3 A, 3 B and the long side 4 B are cut by blade dicing, not possibly affected by the generated heat at the time of the machining.
- the dummy wirings 20 being provided between the side (the long side 4 A) having the curved portion based on the cut-out portion 5 and the constricted portion 6 and the curved corner portions 7 and the wiring networks 9 , 11 , it is surely possible to prevent the wiring networks 9 , 11 from being affected by the heat generated at the time of the laser beam machining.
- the dummy wirings 20 are effective for preventing the insulation performance down, the short circuit, and the like caused by the carbonization of the board material due to the heat generated at the time of the laser beam machining.
- the semiconductor device 1 of the present embodiment it is possible to prevent the insulation performance down between the wiring networks 9 , 11 and the short circuit caused by the effect of the heat generated when machining the curved portions by the laser beam machining. Further, the semiconductor elements 13 , 14 are mounted on a part-mounting region in the second wiring network 11 , raising a concern about the effect of the generated heat as in the second wiring network 11 .
- the second wiring network 11 is arranged sufficiently distant from the portions to be cut by a laser beam, so that the characteristic degradation of the semiconductor elements 13 , 14 due to the generated heat can be prevented. Based on the above, the production yield and reliability of the semiconductor device 1 and the memory card using the same can be improved.
- the semiconductor device 1 of the present invention is effective for the memory card composed simply by the semiconductor device 1 itself without using the case, however, does not necessarily exclude the memory card using the case such as the base card. Even in the case where the memory card is formed by accommodating the semiconductor device in the case, along with the downsizing and density increase of the card, the semiconductor device need to form the cut-out portion and constricted portion therein. Also, in that case, the semiconductor device 1 of the present invention is applicable.
- a circuit board frame 22 including a plurality of device forming regions (memory cord forming regions) 21 is prepared.
- the plurality of the device forming regions 21 correspond to the circuit board 2 , respectively.
- the external connecting terminals 8 are formed by adopting electrolytic plating with respect to the respective device forming regions 21 , 21 , . . . of the circuit board frame 22 .
- the connection pads and the like are also formed by the electrolytic plating as may be necessary.
- the external connecting terminals 8 are formed on a main surface 22 a side of the circuit board frame 22 .
- the semiconductor memory elements 13 are mounted on the second main surface 22 b of the circuit board frame 22 .
- the semiconductor memory elements 13 are mounted on the device forming regions 21 , 21 , . . . , respectively.
- the wire bonding is performed to the semiconductor memory elements 13 , and electrodes of the semiconductor memory elements 13 and the wiring networks of the device forming regions 21 (each circuit board 2 ) are electrically connected via the bonding wires 15 .
- the controller elements 14 are mounted on the semiconductor memory elements 13 , electrodes of the controller elements 14 and the wiring networks of the device forming regions 21 (each circuit board 2 ) are electrically connected via the bonding wires 16 .
- a sealing resin 23 is formed by molding on the second main surface 22 b of the circuit board frame 22 .
- the sealing resin 23 covering the second main surface 22 b of the circuit board frame 22 is formed by molding with a transfer molding or the like so that the semiconductor memory elements 13 and the controller elements 14 mounted on the plurality of device forming regions 21 , respectively, are sealed at a time.
- the handle portions 19 are formed by heaping the part of the sealing resin 23 together when the sealing resin 23 is formed by molding.
- the circuit board frame 22 is sent to the cutting process, and the circuit board frame 22 is cut together with the sealing resin 23 . In this manner, the single piece of semiconductor device 1 with the circuit board 2 is manufactured.
- the cutting process of the circuit board frame 22 as shown in FIG. 8A , firstly, the outer peripheral of the device forming region 21 is cut linearly. In the cutting of the linear portion, the blade dicing exhibiting a higher cutting speed is adopted.
- a numerical reference 24 denotes a cutoff line for the blade dicing.
- the short sides 3 A, 3 B and the long side 4 B of the circuit board 2 except the respective corner portions 7 are processed by the blade dicing only. Accordingly, even the distances to the wiring networks 9 , 11 are small, there is no need to concern about the effect of the generated heat.
- the cut-out portion 5 and the constricted portion 6 are formed by the cutting of the laser beam machining and, at the same time, the corner portions 7 are processed to have an R shape, respectively.
- the laser beam machining of the curved portion raises the concern about the effect of the generated heat, however, here, since the distances from the long side 4 A and the respective corner portions 7 to the wiring networks 9 , 11 are substantially large, allowing preventing the insulation performance down between the wirings and the short circuit caused by the effect of the heat generated at the time of the cutting.
- the insulation performance down between the wirings and the short circuit can be prevented more surely.
- the characteristic degradation of the semiconductor elements 13 , 14 to be mounted on the element mounting region of the second wiring network 11 can be prevented as well.
- the blade dicing and the laser beam machining may be reversed in terms of order.
- the long side 4 A of the device forming region 21 with the cut-out portion 5 and the constricted portion 6 and the respective corner portions 7 are laser-beam machined.
- a full line shows a portion to be cut by the laser beam machining.
- the long side 4 A including the corner portions 7 at both the end thereof is laser-beam machined.
- the short sides 3 A, 3 B and the long side 4 B in the device forming region 21 are blade diced to manufacture the semiconductor device 1 .
- the blade dicing exhibiting a higher cutting speed is adopted to cut the linear portion, and the laser beam machining is adopted only to process the cut-out portion 5 and the constricted portion 6 including the curved portion, respectively, and the corner portions 7 . Accordingly, the processing efficiency in the cutting step can be improved compared with the case where the entire outer periphery of the circuit board 2 is cut by the laser beam machining.
- the long side 4 A and the corner portions 7 have a sufficiently large distance with respect to the wiring networks 9 , 11 , so that the insulation performance down between the wirings, the short circuit, and the characteristic degradation of the semiconductor elements 13 , 14 can be prevented. Accordingly, the semiconductor device 1 with high reliability can be manufactured with high efficiently at a high production yield.
- the semiconductor device of the present invention is not limited to the above-described embodiment and is applicable to various types of semiconductor devices of which at least one side composing the external shape of the circuit board is provided with the curved portion.
- the present invention is not limited to the semiconductor device for the memory card.
- the concrete structure of the semiconductor device and the memory card of the present invention may be modified variously as long as they satisfy the basic structure of the present invention.
- the embodiment may be extended or altered within the scope of the technical spirit of the present invention and the extended or altered embodiment is also within the technical scope of the present invention.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
- Credit Cards Or The Like (AREA)
Abstract
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-098271 filed on Mar. 31, 2006 and the prior Japanese Patent Application No. 2006-277884 field on Oct. 11, 2006; the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a memory card using the same.
- 2. Description of the Related Art
- Semiconductor memory cards having a NAND type flash memory or the like built therein are downsized while having larger capacity. For instance, SD™ memory card is presented in three sizes, a size of a normal SD™ card, a size of a mini SD™ card and a size of a micro SD™ card, in which even the micro SD™ card is expected to have a larger capacity. In an attempt to increase the capacity of the downsized memory card, it is examined and put into practical use that the semiconductor device having a built-in semiconductor element such as a memory element, a controller element or the like forms the memory card without being accommodated in a case such as a base card.
- In order to manufacture a small-sized memory card, a circuit board frame, in which regions to form a plurality of memory cards are arranged in a matrix manner, is prepared at first. An external connecting terminal is formed in each of the card-forming regions by electrolytic plating or the like, and after that a semiconductor element is mounted on a rear surface side. Subsequently, the semiconductor elements and the circuit boards are electrically connected and a sealing resin is formed by molding on the rear surface of the circuit board frame to seal the semiconductor elements mounted on the plurality of card-forming regions all at once.
- The circuit board frame together with the sealing resin is cut in accordance with the card forming regions to manufacture the plurality of memory cards all at once. A cut-out portion, a constricted portion and the like indicating a head or rear direction and an upper or lower direction of the card when the card is equipped into a card slot is provided at an outer peripheral portion of the memory card. In the memory card formed by accommodating the semiconductor device in the case, the cut-out portion, the constricted portion and the like are formed at the case. In the memory card formed by the semiconductor device only without using the case, the cut-out portion, the constricted portion and the like need to be formed at the semiconductor device itself.
- When cutting the circuit board frame, a blade dicing being highly speedy is adopted in general. Since the cut-out portion and the constricted portion have a complicated form including a curved portion, the adoption of a laser beam machining or a water jet machining is under consideration. However, these machining methods have a problem of a low cutting speed compared with the blade dicing. When the laser beam machining or the water jet machining is adopted to cut the entire outline, a machining efficiency down in the cutting step of the circuit board frame is unavoidable.
- The curved portion needs to be cut at a lower speed than the speed to cut the linear portion, in which the machining efficiency downs further. Of the laser machining and the water jet machining effective for cutting the curved portion, the laser machining exhibits a higher cutting efficiency as compared to the water jet machining, whereas a cooling efficiency thereof downs at the time of a low-speed cutting, in which a problem of heat generation is caused at the cut portion. Affected by the heat generated at the time of the cutting, there arise problems such as an insulation performance down between the wirings, a short circuit caused by carbonized resist or core material composing the circuit board, and further an easily-caused characteristic degradation of the semiconductor element.
- A semiconductor device according to an aspect of the present invention includes: a substrate including a first main surface, a second main surface on an opposite of the first main surfaces, and a curved portion provided in at least one side of an external shape thereof; a semiconductor element mounted on at least one of the first and second main surfaces of the substrate; and a wiring network provided on at least one of the first and second main surfaces of the substrate, wherein distance from the side including the curved portion of the substrate to the wiring network is larger than distance from at least one of the other sides of the substrate to the wiring network.
- A semiconductor device according to another aspect of the present invention includes: a substrate including a first main surface, a second main surface on an opposite of the first main surface, and a curved portion provided in at least one side of an external shape thereof; an external connecting terminal formed on the first main surface of the substrate; a first wiring network provided in a region except a region formed the external connecting terminal on the first main surface of the substrate; a second wiring network provided on the second main surface of the substrate; and a semiconductor element mounted on the second main surface of the substrate, wherein distance from the side including the curved portion of the substrate to the first wiring network is larger than distance from at least one of the other sides of the substrate to the first wiring network, and distance from the side including the curved portion of the substrate to the second wiring network is larger than distance from at least one of the other sides of the substrate to the second wiring network.
- A memory card according to an aspect of the present invention includes: a substrate including a first main surface, a second main surface on an opposite of the first main surface, and a curved portion provided in at least one side of an external shape thereof; an external connecting terminal formed on the first main surface of the substrate; a first wiring network provided in a region except a region formed the external connecting terminal on the first main surface of the substrate; an insulating layer formed on the first main surface of the substrate to cover the first wiring network; a second wiring network provided on the second main surface of the substrate; a semiconductor memory element mounted on the second main surface of the substrate; and a sealing resin layer formed on the second main surface of the substrate to seal the semiconductor memory element, wherein distance from the side including the curved portion of the substrate to the first wiring network is larger than distance from at least one of the other sides of the substrate to the first wiring network, and distance from the side including the curved portion of the substrate to the second wiring network is larger than distance from at least one of the other sides of the substrate to the second wiring network.
-
FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. -
FIG. 2 is a plan view showing the semiconductor device shown inFIG. 1 . -
FIG. 3 is a rear view showing the semiconductor device shown inFIG. 1 . -
FIG. 4 is a view showing an example of a second wiring network provided on a second main surface of a circuit board composing the semiconductor device shown inFIG. 1 . -
FIG. 5 is a view showing another example of the second wiring network provided on the second main surface of the circuit board composing the semiconductor device shown inFIG. 1 . -
FIG. 6 is a view showing another example of the circuit board composing the semiconductor device shown inFIG. 1 . -
FIGS. 7A , 7B and 7C are views showing a manufacturing process of the semiconductor device shown inFIG. 1 . -
FIGS. 8A and 8B are plan views showing a cutting step of a circuit board frame in the manufacturing process of the semiconductor device shown inFIG. 1 . -
FIGS. 9A and 9B are plan views showing another cutting step of the circuit board frame in the manufacturing process of the semiconductor device shown inFIG. 1 . - Hereinafter, a mode to embody the present invention will be described with reference to the drawings.
FIG. 1 ,FIG. 2 andFIG. 3 are views showing a structure of a semiconductor device according to an embodiment of the present invention, in whichFIG. 1 is a sectional view of the semiconductor device,FIG. 2 is a plan view (upper view) thereof andFIG. 3 is a rear view thereof. Asemiconductor device 1 shown in these view is composed of a memory card, and thesemiconductor device 1 is used by itself as, for example, a micro SD™ standard memory card (microSD™ card). Thesemiconductor device 1 includes acircuit board 2 serving as a terminal forming substrate and an element mounting substrate. - The
circuit board 2 is formed, for example, by providing a wiring network inside or on a surface of an insulating resin substrate, and specifically, a print circuit board using glass epoxy resin, BT resin (Bsmaleimide-Triazine resin) or the like is applicable. Thecircuit board 2 includes a firstmain surface 2 a to be a terminal forming surface and a secondmain surface 2 b to be an element mounting surface. Thecircuit board 2 has substantially a rectangular shape in appearance. Ashort side 3A corresponds to a head portion when inserting the memory card into a card slot. Anothershort side 3B corresponds to a rear portion of the memory card. - A
long side 4A of thecircuit board 2 is provided with a cut-outportion 5 and aconstricted portion 6 indicating the head, rear, upper and lower direction of the memory card. The cut-outportion 5 is formed by cutting out the corner portion between theshort side 3A and thelong side 4A and a part of thelong side 4A continued therefrom to make theshort side 3A be smaller than theshort side 3B. Theconstricted portion 6 is formed by cutting out a part of thelong side 4A into substantially a trapezoidal shape. The cut-outportion 5 and theconstricted portion 6 have a complicated shape including a curved portion, respectively, and thereby shape thecircuit board 2 into a complicated shape in appearance as well. - The
long side 4A of thecircuit board 2 includes the cut-outportion 5 and theconstricted portion 6 having a curved portion as a part of their shapes, respectively. Further,respective corner portions 7 of thecircuit board 2 are designed to be curved (have an R shape). Although, here, the cut-outportion 5 and theconstricted portion 6 are described separately, these portions may be collectively referred to as a portion formed by cutting out a part of the side composing the external form of thecircuit board 2. Thesemiconductor device 1 is effective when using thecircuit board 2 including the cut-out portion as described above. Further, thesemiconductor device 1 is effective when using thecircuit board 2 including thecurved corner portion 7. - The first
main surface 2 a of thecircuit board 2 has thereon anexternal connecting terminal 8 to be an input/output terminal of the memory card. Further, the firstmain surface 2 a of thecircuit board 2 includes afirst wiring network 9 in the region other than the region where the external connectingterminal 8 is formed. Thefirst wiring network 9 is covered by aninsulating layer 10 using an insulating adhesive seal or insulating adhesive tape, and is insulated thereby. Thefirst wiring network 9 is formed to have a longer distance L11 from thelong side 4A with the cut-outportion 5 and theconstricted portion 6 than distance from at least one of the other sides. - Specifically, the
first wiring network 9 is formed so that the distance L11 from thelong side 4A with the cut-outportion 5 and theconstricted portion 6 to thefirst wiring network 9 becomes larger than a distance L12 from theshort side 3B to thefirst wiring network 9 and a distance L13 from along side 4B to the first wiring network 9 (L11>L12, L11>L13). Note that the distances compared with the distance L11 from thelong side 4A are the distances L12, L13 from theshort side 3B and thelong side 4B, respectively, to which thefirst wiring network 9 is close, and the distance from theshort side 3A through the region formed the external connectingterminal 8 is excluded. The distance L11 from thelong side 4A is larger than the distance from each of the other sides except the side through the formation region of the external connectingterminal 8. - As in the distance L11 from the
long side 4A with the cut-outportion 5 and theconstricted portion 6, thefirst wiring network 9 has larger distances from the R-shapedcorner portions 7 of thecircuit board 2 than the distances (L12 and L13) from theother sides first wiring network 9 is formed so that the distance L11 from thelong side 4A with the cut-outportion 5 and theconstricted portion 6 and the distances from the curved corner portions (corners having a R shape) 7 of thecircuit board 2 become larger than the distances (L12, L13) from theother sides - On a second
main surface 2 b of thecircuit board 2, asecond wiring network 11 including a connection pad at the time of a wire bonding and the like is provided.FIG. 4 shows a configuration example of thesecond wiring network 11. As in thefirst wiring network 9, thesecond wiring network 11 is formed so that a distance L21 from thelong side 4A with the cut-outportion 5 and theconstricted portion 6 becomes larger than the distances from the other sides, namely theshort side 3A, theshort side 3B, and thelong side 4B. - The
second wiring network 11 includesplating lead wires 12 to form the external connectingterminal 8 and the like by electrolytic plating. Theplating lead wires 12 are drawn out toward the sides except thelong side 4A with the cut-outportion 5 and theconstricted portion 6, for example, toward theshort side 3B and thelong side 4B. InFIG. 4 , theplating lead wires 12 are drawn out to theshort side 3B and thelong side 4B, proving that the distances from theshort side 3B and thelong side 4B to thesecond wiring network 11 are 0 (zero). Accordingly, thesecond wiring network 11 is formed so that the distance L21 from thelong side 4A becomes larger than the distance from theshort side 3A, further the distances (virtually 0 (zero)) from theshort side 3B and thelong side 4B. - As in the distance L21 from the
long side 4A with the cut-outportion 5 and theconstricted portion 6, thesecond wiring network 11 has larger distances from the R-shapedcorner portions 7 of thecircuit board 2 than the distance (for example, L22) from the other side. Thesecond wiring network 11 is formed so that the distance L21 from thelong side 4A with the cut-outportion 5 and theconstricted portion 6 as well as the distances from the curved corner portions (corners having a R shape) 7 of thecircuit board 2 become larger than the distance from each of theother sides - The
second wiring network 11 is drawn out to theshort side 3B and thelong side 4B. Meanwhile, a region having no wiring formed (non-wiring region X) is provided between thelong side 4A with the cut-outportion 5 and theconstricted portion 6 and thesecond wiring network 11. The non-wiring region X is also provided between the curved-corner portions 7 and thesecond wiring network 11, respectively. As will be described later, the non-wiring regions X are provided in a corresponding manner to the portions of which external shapes are processed by adopting a laser beam machining. Specifically, the non-wiring regions X are set between thesecond wiring network 11 and the portions (thelong side 4A and the respective corner portions 7) of thecircuit board 2, of which external shapes are processed by employing the laser beam machining. This is equally applied to thefirst wiring network 9. - In the
plating lead wires 12, the portions existing in the vicinity of theshort side 3B and thelong side 4B may be removed by etching or the like as shown inFIG. 5 , after forming the external connectingterminal 8 and the like by carrying out the electrolytic plating to thecircuit board 2. In that case, as in the other wirings, theplating lead wires 12 are to exist at the portions distant a predetermined distance from the respective sides (theshort side 3B, thelong side 4B and the like) composing the external shape of thecircuit board 2. Also, in the above-described case, thesecond wiring network 11 is formed so that the distance L21 from thelong side 4A becomes larger than the respective distances from theshort side 3A, theshort side 3B and thelong side 4B. - Further, in addition to that the distances from the
long side 4A and thecorner portions 7 respectively of the first andsecond wiring networks other sides second wiring networks 11 and thelong side 4A and thecorner portions 7, respectively, is also effective.FIG. 6 shows one example of dummy wirings 20 provided on the secondmain surface 2 b of thecircuit board 2. In the secondmain surface 2 b of thecircuit board 2, thedummy wiring 20 is provided between thelong side 4A having the curved portions based on the cut-outportion 5 and theconstricted portion 6 and thecurved corner portions 7 and thesecond wiring network 11, respectively. - The dummy wirings 20 do not serve as electric wirings but to serve by protecting the
second wiring network 11 against an inconvenience (carbonization of a board material and the like) caused by heat generated at the time of the laser beam machining. The dummy wirings 20 exist independently of thesecond wiring network 11. Even when the laser beam machining is carried out to thelong side 4A and thecorner portions 7 and thereby the board material of the machined portions is carbonized, the dummy wirings 20 halt the carbonization by themselves. Accordingly, thesecond wiring network 11 is surely prevented from being adversely affected by the carbonization of the board material. The dummy wirings 20 may be formed with respect to the firstmain surface 2 a of thecircuit board 2 as well. Thedummy wiring 20 may be arranged between various laser-beam machined portions and the wiring network, and the wiring network is prevented from the adverse affect also in that case. - First and
second semiconductor elements main surface 2 b of thecircuit board 2. Thefirst semiconductor element 13 is a semiconductor memory element such as of a NAND-type flash memory. The firstsemiconductor memory element 13 is adhered to the secondmain surface 2 b of thecircuit board 2 via a not-shown adhesive layer. The number of the firstsemiconductor memory element 13 to be mounted is not limited to one and two or more is also acceptable. Thesecond semiconductor element 14 is, for example, a controller element. Thecontroller element 14 is stacked and adhered on thesemiconductor memory element 13 via a not-shown adhesive layer. - Respective electrode pads (not-shown) of the
semiconductor memory element 13 and thecontroller element 14 are electrically connected to a connection pad provided to thesecond wiring network 11 viabonding wires second wiring network 11 is electrically connected to the external connectingterminal 8 and thefirst wiring network 9 via a not-shown internal wiring (a through hole and so on) of thecircuit board 2. On the secondmain surface 2 b of thecircuit board 2 having thesemiconductor memory element 13 and thecontroller element 14 mounted thereon, a sealingresin layer 17 such as of epoxy resin is formed by molding. Thesemiconductor memory element 13 and thecontroller element 14 are sealed by the sealingresin layer 17. - The
semiconductor memory element 13 and thecontroller element 14 mounted on the secondmain surface 2 b of thecircuit board 2 are sealed in a unified manner by the sealingresin layer 17 to form the semiconductor device (memory card) 1. The sealingresin layer 17 is formed by molding with respect to a plurality of thecircuit boards 2 all at a time, as will be described later. The sealingresin layer 17 is cut together with thecircuit board 2. In the sealingresin layer 17, the cut-outportion 5 and theconstricted portion 6 having the same shape as of thecircuit board 2 are formed. The same is equally applied to the respective corner portions of the sealingresin layer 17, and the same curved shape (R shape) as of the corner portions of thecircuit board 2 are given thereto. - A
slant portion 18 formed by cutting parts of the sealingresin layer 17 and thecircuit board 2 is provided at the head side (theshort side 3A side) of the sealingresin layer 17 with an aim to facilitate the insertion/removal of the memory card. Theslant portion 18 is provided on the surface side (the firstmain surface 2 a side of the circuit board 2) of the memory card. On the rear side (theshort side 3B side) of the sealingresin layer 17, ahandle portion 19 formed by partially heaping the sealing resin is provided. Thehandle portion 19 is provided on the rear surface side (the secondmain surface 2 b side of the circuit board 2) of the memory card. - The
semiconductor device 1 of the present embodiment forms a memory card (for example, a micro SD™ card) by itself without using any case accommodating the semiconductor device such as a base card. Thesemiconductor device 1 is a memory card exposing its insulatinglayer 10 and sealingresin layer 17 outside without using a case. Therefore, the cut-outportion 5 and theconstricted portion 6 indicating the head/rear and surface/rear surface directions and the like of the memory card are provided in thesemiconductor device 1 itself. The cut-outportion 5 and theconstricted portion 6 are formed by cutting thecircuit board 2 together with the sealingresin layer 17. - The cut-out
portion 5 and theconstricted portion 6 are formed partially by a curved line, making a blade dicing be difficult. Therefore, the cut-outportion 5 and theconstricted portion 6 are cut by adopting, for example, a laser beam machining. The laser beam machining may be adopted for the machining of the entirelong side 4A with the cut-outportion 5 and theconstricted portion 6. In that case, the curved portion needs to be cut at a lower speed than that to cut the linear portion. Therefore, a cooling efficiency at the time of the laser beam machining downs, raising a concern about an effect of heat generated at the cut portion. - In the
semiconductor device 1 of the present embodiment, the distance from the side including the curved portions such as the cut-outportion 5 and the constricted portion 6 (here, thelong side 4A) to the first andsecond wiring networks second wiring networks second wiring networks semiconductor elements wiring networks semiconductor elements wiring networks - As for the
curved corner portions 7, as in the distances L11, L21 from thelong side 4A, the distances therefrom to the first andsecond wiring networks corner portions 7 can be prevented. In order to prevent the effect of the heat generated at the time of the laser beam machining with high reproducibility, preferably, the distances from the sides to be subject to the laser beam machining (laser-beam machined portions) to thewiring networks long side 4A and thecorner portions 7 to the first andsecond wiring networks - The
second wiring network 11 includes theplating lead wires 12. Theplating lead wire 12 needs to be drawn out to the side of thecircuit board 2. In the present embodiment, theplating lead wires 12 are drawn out toward the sides except thelong side 4A with the cut-outportion 5 and the constricted portion 6 (theshort side 3B and thelong side 4B). Therefore, the heat generated at the time of the laser beam machining does not possibly affect theplating lead wires 12. As will be described later, the linershort sides long side 4B are cut by blade dicing, not possibly affected by the generated heat at the time of the machining. - Further, with the dummy wirings 20 being provided between the side (the
long side 4A) having the curved portion based on the cut-outportion 5 and theconstricted portion 6 and thecurved corner portions 7 and thewiring networks wiring networks - According to the
semiconductor device 1 of the present embodiment, it is possible to prevent the insulation performance down between thewiring networks semiconductor elements second wiring network 11, raising a concern about the effect of the generated heat as in thesecond wiring network 11. In the present embodiment, thesecond wiring network 11 is arranged sufficiently distant from the portions to be cut by a laser beam, so that the characteristic degradation of thesemiconductor elements semiconductor device 1 and the memory card using the same can be improved. - Note that the
semiconductor device 1 of the present invention is effective for the memory card composed simply by thesemiconductor device 1 itself without using the case, however, does not necessarily exclude the memory card using the case such as the base card. Even in the case where the memory card is formed by accommodating the semiconductor device in the case, along with the downsizing and density increase of the card, the semiconductor device need to form the cut-out portion and constricted portion therein. Also, in that case, thesemiconductor device 1 of the present invention is applicable. - Subsequently, the description will be given of a manufacturing process of the above-described
semiconductor device 1. First, as shown inFIG. 7A , acircuit board frame 22 including a plurality of device forming regions (memory cord forming regions) 21 is prepared. The plurality of thedevice forming regions 21 correspond to thecircuit board 2, respectively. The external connectingterminals 8 are formed by adopting electrolytic plating with respect to the respectivedevice forming regions circuit board frame 22. At this time, the connection pads and the like are also formed by the electrolytic plating as may be necessary. The external connectingterminals 8 are formed on amain surface 22 a side of thecircuit board frame 22. - Subsequently, as shown in
FIG. 7B , thesemiconductor memory elements 13 are mounted on the secondmain surface 22 b of thecircuit board frame 22. Thesemiconductor memory elements 13 are mounted on thedevice forming regions semiconductor memory elements 13, and electrodes of thesemiconductor memory elements 13 and the wiring networks of the device forming regions 21 (each circuit board 2) are electrically connected via thebonding wires 15. Further, after thecontroller elements 14 are mounted on thesemiconductor memory elements 13, electrodes of thecontroller elements 14 and the wiring networks of the device forming regions 21 (each circuit board 2) are electrically connected via thebonding wires 16. - After that, as shown in
FIG. 7C , a sealingresin 23 is formed by molding on the secondmain surface 22 b of thecircuit board frame 22. In the resin molding process, the sealingresin 23 covering the secondmain surface 22 b of thecircuit board frame 22 is formed by molding with a transfer molding or the like so that thesemiconductor memory elements 13 and thecontroller elements 14 mounted on the plurality ofdevice forming regions 21, respectively, are sealed at a time. Thehandle portions 19 are formed by heaping the part of the sealingresin 23 together when the sealingresin 23 is formed by molding. - The
circuit board frame 22 is sent to the cutting process, and thecircuit board frame 22 is cut together with the sealingresin 23. In this manner, the single piece ofsemiconductor device 1 with thecircuit board 2 is manufactured. In the cutting process of thecircuit board frame 22, as shown inFIG. 8A , firstly, the outer peripheral of thedevice forming region 21 is cut linearly. In the cutting of the linear portion, the blade dicing exhibiting a higher cutting speed is adopted. Anumerical reference 24 denotes a cutoff line for the blade dicing. Theshort sides long side 4B of thecircuit board 2 except therespective corner portions 7 are processed by the blade dicing only. Accordingly, even the distances to thewiring networks - Subsequently, as shown in
FIG. 8B , the cut-outportion 5 and theconstricted portion 6 are formed by the cutting of the laser beam machining and, at the same time, thecorner portions 7 are processed to have an R shape, respectively. As described above, the laser beam machining of the curved portion raises the concern about the effect of the generated heat, however, here, since the distances from thelong side 4A and therespective corner portions 7 to thewiring networks semiconductor elements second wiring network 11 can be prevented as well. - Note that the blade dicing and the laser beam machining may be reversed in terms of order. In other words, as shown in
FIG. 9A , thelong side 4A of thedevice forming region 21 with the cut-outportion 5 and theconstricted portion 6 and therespective corner portions 7 are laser-beam machined. In the drawing, a full line shows a portion to be cut by the laser beam machining. In the processing of thelong side 4A, it is acceptable to adopt the laser beam machining only to form the cut-outportion 5 and theconstricted portion 6, however, when the laser beam machining is adopted to process the entirelong side 4A including the above-stated portions, processing efficiency is improved. Thelong side 4A including thecorner portions 7 at both the end thereof is laser-beam machined. After that, as shown inFIG. 9B , theshort sides long side 4B in thedevice forming region 21 are blade diced to manufacture thesemiconductor device 1. - According to the manufacturing process of the
semiconductor device 1, the blade dicing exhibiting a higher cutting speed is adopted to cut the linear portion, and the laser beam machining is adopted only to process the cut-outportion 5 and theconstricted portion 6 including the curved portion, respectively, and thecorner portions 7. Accordingly, the processing efficiency in the cutting step can be improved compared with the case where the entire outer periphery of thecircuit board 2 is cut by the laser beam machining. On the basis of the above, thelong side 4A and thecorner portions 7 have a sufficiently large distance with respect to thewiring networks semiconductor elements semiconductor device 1 with high reliability can be manufactured with high efficiently at a high production yield. - Note that the semiconductor device of the present invention is not limited to the above-described embodiment and is applicable to various types of semiconductor devices of which at least one side composing the external shape of the circuit board is provided with the curved portion. The present invention is not limited to the semiconductor device for the memory card. Further, the concrete structure of the semiconductor device and the memory card of the present invention may be modified variously as long as they satisfy the basic structure of the present invention. Furthermore, the embodiment may be extended or altered within the scope of the technical spirit of the present invention and the extended or altered embodiment is also within the technical scope of the present invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/693,096 US8110434B2 (en) | 2006-03-31 | 2010-01-25 | Semiconductor device and memory card using the same |
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Application Number | Priority Date | Filing Date | Title |
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JP2006-098271 | 2006-03-31 | ||
JP2006098271 | 2006-03-31 | ||
JP2006277884A JP4843447B2 (en) | 2006-03-31 | 2006-10-11 | Semiconductor device and memory card using the same |
JP2006-277884 | 2006-10-11 |
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US12/693,096 Continuation US8110434B2 (en) | 2006-03-31 | 2010-01-25 | Semiconductor device and memory card using the same |
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US20070228509A1 true US20070228509A1 (en) | 2007-10-04 |
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US11/691,716 Active 2027-07-24 US7679174B1 (en) | 2006-03-31 | 2007-03-27 | Semiconductor device and memory card using the same |
US12/693,096 Active 2027-06-23 US8110434B2 (en) | 2006-03-31 | 2010-01-25 | Semiconductor device and memory card using the same |
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US12/693,096 Active 2027-06-23 US8110434B2 (en) | 2006-03-31 | 2010-01-25 | Semiconductor device and memory card using the same |
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Also Published As
Publication number | Publication date |
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US7679174B1 (en) | 2010-03-16 |
JP4843447B2 (en) | 2011-12-21 |
TW200810025A (en) | 2008-02-16 |
US8110434B2 (en) | 2012-02-07 |
US20100120203A1 (en) | 2010-05-13 |
TWI337391B (en) | 2011-02-11 |
JP2007293800A (en) | 2007-11-08 |
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