JP2009016714A - 半導体装置のアンダーフィルの充填方法 - Google Patents
半導体装置のアンダーフィルの充填方法 Download PDFInfo
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- JP2009016714A JP2009016714A JP2007179461A JP2007179461A JP2009016714A JP 2009016714 A JP2009016714 A JP 2009016714A JP 2007179461 A JP2007179461 A JP 2007179461A JP 2007179461 A JP2007179461 A JP 2007179461A JP 2009016714 A JP2009016714 A JP 2009016714A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
【解決手段】 半導体チップの一面に2次元的に配列された複数の電極を、基板上の対応する導電性領域に接合するステップと、半導体チップの一面と基板との間に液状化されたアンダーフィル用樹脂を注入するステップと、一定の圧力下においてアンダーフィル用樹脂をガラス転移温度以上の温度で溶融しキュアするステップとを有する。これにより、アンダーフィル用樹脂内のボイドを消滅させる。
【選択図】 図1
Description
110:主面
120:電極
130:バンプ
200:基板
210:上面
220:電極
230:半田バンプ
240:内部配線
250:裏面
260:外部電極
270:半田ボール
300:アンダーフィル用樹脂
400:半導体パッケージ
410:外部端子
500:第1の半導体パッケージ
600:第2の半導体パッケージ
Claims (10)
- 半導体チップの一面に2次元的に配列された複数の電極を、基板上の対応する導電性領域に接合するステップと、
半導体チップの一面と基板との間に液状化されたアンダーフィル用樹脂を注入するステップと、
一定の圧力下において前記アンダーフィル用樹脂を溶融し前記アンダーフィル用樹脂をキュアするステップと、
を有する半導体装置の製造方法。 - 前記キュアするステップは、前記アンダーフィル用樹脂をガラス転移温度以上に加熱する、請求項1に記載の半導体装置の製造方法。
- 前記アンダーフィル用樹脂は、シリカが充填されたエポキシ樹脂である、請求項1に記載の半導体装置の製造方法。
- 前記アンダーフィル用樹脂が溶融されたときの粘度は、60Pa・s以上である、請求項3に記載の半導体装置の製造方法。
- 前記半導体チップの一面と基板表面との間隔は、50ミクロン以下である、請求項1ないし4いずれか1つに記載の半導体装置の製造方法。
- 半導体チップの複数の電極は、50ミクロン以下のピッチで配列されている、請求項1ないし5いずれか1つに記載の半導体装置の製造方法。
- 製造方法はさらに、アンダーフィル用樹脂が注入された基板をチャンバー内に配置するステップを含み、前記キュアするステップは、前記チャンバー内において圧力を印加しつつ前記アンダーフィル用樹脂を溶融する、請求項1に記載の半導体装置の製造方法。
- 前記注入するステップは、半導体チップの1つの側面側からまたは対角線の方向からアンダーフィル用樹脂を注入する、請求項1に記載の半導体装置の製造方法。
- 半導体パッケージの一面に2次元的に配列された複数の電極を、基板上の対応する導電性領域に接合するステップと、
半導体パッケージの一面と基板との間にアンダーフィル用樹脂を供給するステップと、
一定の圧力下において前記アンダーフィル用樹脂を溶融し前記アンダーフィル用樹脂をキュアするステップと、
を有する半導体装置の製造方法。 - 1の半導体パッケージの一面に2次元的に配列された複数の電極を、他の半導体パッケージ上の対応する導電性領域に接合するステップと、
1の半導体パッケージの一面と他の半導体パッケージの一面との間にアンダーフィル用樹脂を供給するステップと、
一定の圧力下において前記アンダーフィル用樹脂を溶融し前記アンダーフィル用樹脂をキュアするステップと、
を有する半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007179461A JP4569605B2 (ja) | 2007-07-09 | 2007-07-09 | 半導体装置のアンダーフィルの充填方法 |
US12/168,637 US20090017582A1 (en) | 2007-07-09 | 2008-07-07 | Method for manufacturing semiconductor device |
PCT/US2008/069479 WO2009009566A2 (en) | 2007-07-09 | 2008-07-09 | Method for manufacturing semiconductor device |
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JP2007179461A JP4569605B2 (ja) | 2007-07-09 | 2007-07-09 | 半導体装置のアンダーフィルの充填方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010127573A Division JP2010232671A (ja) | 2010-06-03 | 2010-06-03 | 半導体装置のアンダーフィル充填方法 |
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Publication Number | Publication Date |
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JP2009016714A true JP2009016714A (ja) | 2009-01-22 |
JP4569605B2 JP4569605B2 (ja) | 2010-10-27 |
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US (1) | US20090017582A1 (ja) |
JP (1) | JP4569605B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011003876A (ja) * | 2009-06-22 | 2011-01-06 | Korea Electronics Telecommun | 半導体パッケージの製造方法及びこれによって製造された半導体パッケージ |
JP2011040512A (ja) * | 2009-08-10 | 2011-02-24 | Murata Mfg Co Ltd | 回路基板の製造方法 |
KR20120060486A (ko) * | 2010-12-02 | 2012-06-12 | 삼성전자주식회사 | 적층 패키지 구조물 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010245341A (ja) * | 2009-04-07 | 2010-10-28 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
JP2013236039A (ja) * | 2012-05-11 | 2013-11-21 | Renesas Electronics Corp | 半導体装置 |
TWI525721B (zh) * | 2013-08-16 | 2016-03-11 | 印鋐科技有限公司 | 用於電子元件的製造方法與製造設備 |
CN114068472A (zh) * | 2020-08-06 | 2022-02-18 | 力成科技股份有限公司 | 封装结构及其制造方法 |
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2008
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JPH11186322A (ja) * | 1997-10-16 | 1999-07-09 | Fujitsu Ltd | フリップチップ実装用基板及びフリップチップ実装構造 |
JP2004208326A (ja) * | 2000-03-17 | 2004-07-22 | Matsushita Electric Ind Co Ltd | 電気素子内蔵モジュール及びその製造方法 |
JP2002198383A (ja) * | 2000-12-27 | 2002-07-12 | Sanyu Rec Co Ltd | 電子部品の製造方法及び装置 |
JP2003128881A (ja) * | 2001-10-18 | 2003-05-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007103772A (ja) * | 2005-10-06 | 2007-04-19 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2011003876A (ja) * | 2009-06-22 | 2011-01-06 | Korea Electronics Telecommun | 半導体パッケージの製造方法及びこれによって製造された半導体パッケージ |
JP2011040512A (ja) * | 2009-08-10 | 2011-02-24 | Murata Mfg Co Ltd | 回路基板の製造方法 |
KR20120060486A (ko) * | 2010-12-02 | 2012-06-12 | 삼성전자주식회사 | 적층 패키지 구조물 |
JP2012119688A (ja) * | 2010-12-02 | 2012-06-21 | Samsung Electronics Co Ltd | 積層パッケージ構造物、パッケージオンパッケージ素子、およびパッケージオンパッケージ素子製造方法 |
US9520387B2 (en) | 2010-12-02 | 2016-12-13 | Samsung Electronics Co., Ltd. | Stacked package structure and method of forming a package-on-package device including an electromagnetic shielding layer |
KR101711045B1 (ko) * | 2010-12-02 | 2017-03-02 | 삼성전자 주식회사 | 적층 패키지 구조물 |
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US20090017582A1 (en) | 2009-01-15 |
JP4569605B2 (ja) | 2010-10-27 |
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