JP2008547228A - ４．５ｆ２ｄｒａｍセルのための接地されたゲートを備えたトレンチ分離トランジスタおよびそれの製造方法 - Google Patents

４．５ｆ２ｄｒａｍセルのための接地されたゲートを備えたトレンチ分離トランジスタおよびそれの製造方法 Download PDF

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JP2008547228A
JP2008547228A JP2008518327A JP2008518327A JP2008547228A JP 2008547228 A JP2008547228 A JP 2008547228A JP 2008518327 A JP2008518327 A JP 2008518327A JP 2008518327 A JP2008518327 A JP 2008518327A JP 2008547228 A JP2008547228 A JP 2008547228A
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substrate
concave
memory device
memory
gate
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ジェングリン，ワーナー
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マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
JP2008518327A 2005-06-24 2006-06-21 ４．５ｆ２ｄｒａｍセルのための接地されたゲートを備えたトレンチ分離トランジスタおよびそれの製造方法 Pending JP2008547228A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/166,721 US7902598B2 (en) 2005-06-24 2005-06-24 Two-sided surround access transistor for a 4.5F2 DRAM cell
PCT/US2006/024025 WO2007002117A2 (en) 2005-06-24 2006-06-21 Trench isolation transistor with grounded gate for a 4.5f2 dram cell and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2008547228A true JP2008547228A (ja) 2008-12-25

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JP2008518327A Pending JP2008547228A (ja) 2005-06-24 2006-06-21 ４．５ｆ２ｄｒａｍセルのための接地されたゲートを備えたトレンチ分離トランジスタおよびそれの製造方法

Country Status (7)

Country Link
US (3) US7902598B2 (ko)
EP (1) EP1897134B1 (ko)
JP (1) JP2008547228A (ko)
KR (1) KR101331748B1 (ko)
CN (1) CN101208795B (ko)
TW (1) TWI360202B (ko)
WO (1) WO2007002117A2 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012084619A (ja) * 2010-10-07 2012-04-26 Elpida Memory Inc 半導体装置および半導体装置の製造方法
JP2012134395A (ja) * 2010-12-22 2012-07-12 Elpida Memory Inc 半導体装置および半導体装置の製造方法

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KR101952272B1 (ko) * 2012-11-06 2019-02-26 삼성전자주식회사 반도체 기억 소자
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JP6583151B2 (ja) * 2016-06-09 2019-10-02 株式会社デンソー 半導体装置の製造方法
WO2018182726A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Transistors with oxygen exchange layers in the source and drain
CN107425072A (zh) * 2017-09-06 2017-12-01 睿力集成电路有限公司 一种半导体存储器的器件结构
CN110875254B (zh) * 2018-09-04 2022-04-19 长鑫存储技术有限公司 半导体器件的形成方法
US11189623B2 (en) * 2018-12-18 2021-11-30 Micron Technology, Inc. Apparatuses, memory devices, and electronic systems
US20210167068A1 (en) * 2019-12-03 2021-06-03 Nanya Technology Corporation Memory device
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Also Published As

Publication number Publication date
TWI360202B (en) 2012-03-11
EP1897134A2 (en) 2008-03-12
KR20080026631A (ko) 2008-03-25
US20130248958A1 (en) 2013-09-26
EP1897134B1 (en) 2014-08-27
KR101331748B1 (ko) 2013-11-20
US20110133270A1 (en) 2011-06-09
TW200707653A (en) 2007-02-16
CN101208795A (zh) 2008-06-25
WO2007002117A3 (en) 2007-03-15
US7902598B2 (en) 2011-03-08
WO2007002117A2 (en) 2007-01-04
CN101208795B (zh) 2010-05-19
US20060289919A1 (en) 2006-12-28
US8836023B2 (en) 2014-09-16
US8933508B2 (en) 2015-01-13

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