WO2018182726A1 - Transistors with oxygen exchange layers in the source and drain - Google Patents

Transistors with oxygen exchange layers in the source and drain Download PDF

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Publication number
WO2018182726A1
WO2018182726A1 PCT/US2017/025537 US2017025537W WO2018182726A1 WO 2018182726 A1 WO2018182726 A1 WO 2018182726A1 US 2017025537 W US2017025537 W US 2017025537W WO 2018182726 A1 WO2018182726 A1 WO 2018182726A1
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WO
WIPO (PCT)
Prior art keywords
channel
oxygen exchange
drain
exchange layer
depositing
Prior art date
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PCT/US2017/025537
Other languages
French (fr)
Inventor
Gilbert Dewey
Van H. Le
Abhishek A. Sharma
Shriram SHIVARAMAN
Ravi Pillarisetty
Tahir Ghani
Original Assignee
Intel Corporation
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Priority to PCT/US2017/025537 priority Critical patent/WO2018182726A1/en
Publication of WO2018182726A1 publication Critical patent/WO2018182726A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • This disclosure generally relates to transistors.
  • MOSFETs Metal-oxide semiconductor field-effect transistors
  • MOSFETs can represent transistor devices can be used for logic and memory. It may be desirable to have a transistor device that turns on at a current level that is significantly higher than a current level at which the transistor device turns off.
  • a transistor device having a high on to off current ratio can have be faster and use lower power (for example, lower standby power) than a transistor device having a lower on to off current ratio.
  • Such transistor devices (for example, MOSFET devices) may need to be fabricated in silicon using high temperature processing, for example, in order to gate the source and the drain of the transistor device.
  • FIG. 1 shows a diagram of a thin film transistor, having at least a source, a drain, and a gate.
  • FIG. 2A shows a diagram of a partial structure of a thin film transistor, in accordance with one or more example embodiments of the disclosure.
  • FIG. 2B shows a diagram of another partial structure of a thin film transistor, having oxygen exchange layers, in accordance with one or more example embodiments of the disclosure.
  • FIG. 2C shows a diagram of another partial structure of a thin film transistor having a source and a drain, in accordance with one or more example embodiments of the disclosure.
  • FIG. 2D shows a diagram of another partial structure of a thin film transistor having depletion layers, in accordance with one or more example embodiments of the disclosure.
  • FIG. 3 shows an example flowchart for the fabrication of a thin film transistor, in accordance with example embodiments of the disclosure.
  • FIG. 4 shows a diagram of an example system, in accordance with example embodiments of the disclosure.
  • the term "horizontal” as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation.
  • the term “vertical,” as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as “on,” “above,” “below,” “bottom,” “top,” “side” (as in “sidewall”), “higher,” “lower,” “upper,” “over,” and “under,” may be referenced with respect to a horizontal plane, where the horizontal plane can include an x- y plane, a x-z plane, or a y-z plane, as the case may be.
  • processing as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.
  • thin film transistors can include metal-oxide semiconductor field-effect transistors (MOSFETs).
  • MOSFETs metal-oxide semiconductor field-effect transistors
  • the thin film transistors can be fabricated on a silicon substrate.
  • the thin film transistors can be made in a semiconducting material, such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the thin film transistor may need to comply with low temperature processing, such as low temperature processing used in backend-of-line (BEOL) processing.
  • BEOL backend-of-line
  • BEOL processing can refer to a portion of Integrated circuit (IC) fabrication, where individual devices (transistors, capacitors, resistors, and the like) are interconnected with wiring on a wafer.
  • the thin film transistor may need to comply with low temperature processing for compatibility with existing logic and memory devices in silicon. For example, functionality can be added to existing logic and memory devices in silicon by adding these extra transistors in different metal layers or in the BEOL processing.
  • front-end-of-line (FEOL) processing methods can refer to methods for the formation of transistors directly in silicon.
  • the processing may need to be performed at relatively lower temperatures, for example, less than 450 degrees centigrade. Thin film transistors made at such lower temperatures may need to meet predetermined contact resistance and gating properties without the use of high temperature processing, as in FEOL processing.
  • the use of high temperature annealing can be used to heal and make transistors more efficient.
  • high temperature processing can crystallize silicon, activate dopants in various regions of the transistor, and/or heal damage in the gate dielectric of a transistor.
  • thin film transistors may need to be deposited at low temperatures on a non-native substrate (that is, a substrate that comprises a material that cannot withstand high temperature processing steps). Such thin film transistors may nevertheless need to have high device on to off ratios.
  • a non-native substrate that is, a substrate that comprises a material that cannot withstand high temperature processing steps.
  • Such thin film transistors may nevertheless need to have high device on to off ratios.
  • One challenge in the fabrication of low temperature devices can involve achieving suitable contacts.
  • FEOL processing a high dopant concentration in the source and drain of a transistor can permit an increase in the level of current flowing in transistor during operation.
  • devices fabricated using BEOL processing may not have the option to be implanted with dopants or otherwise have impurities (for example, phosphorous or boron impurities) that can be annealed at high temperatures and thereby activated.
  • the systems, methods, and apparatus are directed to improving the contact resistance associated with thin film transistors.
  • the disclosure can permit gating of the semiconducting material from low off current levels to high on current levels.
  • a high on current in the transistor can be limited, in part, by the access resistance, or external resistance to the channel of the transistor.
  • one or more elements of the transistor that are outside of the gated portion of the transistor can be implicated in increasing the access resistance.
  • the channel of the transistor can include thin film transistor material, which can be a semiconducting oxide.
  • the semiconducting oxide can include an amorphous semiconducting oxide that can be deposited at low temperature.
  • the thin film transistor material can include a semiconducting oxide that can be indium gallium zinc oxide (IGZO).
  • IGZO can have a relatively wide band gap relative to silicon.
  • the band gap of silicon can be approximately 1.1 electron volts (eV), while the bandgap of IGZO can be approximately 3 eV.
  • contacting a channel comprising a semiconducting oxide with a wide band gap may involve overcoming an energy barrier that may otherwise prevent the injection of carriers into the semiconducting oxide.
  • a channel comprising a semiconducting oxide with a wide band gap may involve overcoming an energy barrier that may otherwise prevent the injection of carriers into the semiconducting oxide.
  • a thin film transistor material such as a semiconducting oxide having a larger band gap
  • it can become harder to achieve a low contact resistance to the channel of the transistor.
  • a low resistance contact to small band gap semiconductors like, for example, Indium Arsenide (having a band gap of approximately 0.36 eV), can be relatively straightforward with conventional semiconductor processing techniques.
  • the contact resistance can increase.
  • the material may generally serve as an insulator, and the contact resistance can increase further.
  • the current flow through the material can be negligible.
  • a metal may not have a band gap, thereby the metal can have many carriers.
  • many thin film semiconducting oxides can include multi-metal systems (for example, indium, gallium, zinc, and the like) and an oxide.
  • the systems, methods, and apparatus disclosed herein describe reducing the oxide component of the semiconducting oxides comprising the channel of the transistor in order to make the semiconducting oxides more metallic.
  • the semiconducting oxides can have a narrower band gap and have more carriers; further the contact resistance to the semiconducting oxides will be exponentially reduced.
  • reactive metals can be used between the source and/or drain (or contacts, as the case may be) and the channel of the transistor.
  • reactive metals can include metals having a relatively low work function.
  • reactive metals can include aluminum, titanium, hafnium, zirconium, and the like. In one embodiment, such reactive metals may bond to oxygen and nitrogen or other elements to become more stable.
  • the reactive metal can be deposited beneath the source and/or drain region of the transistor before depositing the metal contact to the semiconducting oxide (for example, the IGZO) serving as the channel to the transistor.
  • the reactive metal can serve as an oxygen exchange layer. That is, the reactive metal can remove oxygen from the semiconducting oxide. It can pull oxygen out of semiconducting oxide (for example, the IGZO) thin film material and it can make the semiconducting oxide become more metallic and more conductive.
  • the contact resistance to the semiconducting oxide can be reduced. With less oxygen, the semiconducting oxide can become more metallic, can have more charge, and higher mobility. It can result in lower source drain resistance, lower contact resistance, than the thin film transistor without this reactive metal in the contact.
  • the band gap can be reduced (for example, in the case of a channel comprising a semiconductor oxide layer of IGZO having a bandgap of approximately 3.2 eV, the bandgap of the channel comprising the semiconducting oxide having oxygen removed can be reduced to less than approximately 2 eV).
  • the reduction in the bandgap in the semiconducting oxide can allow more carriers to exist in the channel comprising semiconducting oxide having oxygen removed.
  • the reduced bandgap, increased carrier concentration, and the increased mobility can result in a reduced contact resistance and improved transistor performance.
  • FIG. 1 shows a diagram of an example transistor, for example, a thin film transistor 101 in accordance with one or more example embodiments of the disclosure.
  • the transistor 101 can include a substrate 100.
  • the substrate 100 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate 100 can include a silicon substrate.
  • the substrate 100 can include a p-doped silicon substrate.
  • the substrate 100 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate 100 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • the transistor 101 can include a channel.
  • the channel 105 can include an amorphous oxide semiconductor.
  • the channel 105 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel 105 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel 105 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel 105 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel 105 can be approximately 4 nm to approximately 50 nm thick, with example thicknesses of approximately 10 nm to approximately 30 nm thick.
  • the channel 105 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.
  • the transistor 101 can include a source 110.
  • the source 110 can include a metal.
  • the source 110 can include a contact metal.
  • the source 110 can serve as a Schottky source.
  • the source 110 can include a nonreactive metal.
  • the source 110 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the source 110 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the source 110 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the source 1 10 can be deposited using PVD, CVD, MOCVD, and/or ALD.
  • the transistor 101 can include a drain 1 15.
  • the drain 115 can include a metal.
  • the drain 1 15 can include a contact metal.
  • the drain 115 can serve as a Schottky drain.
  • the drain 1 15 can include a nonreactive metal.
  • a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source 110 and/or drain 115.
  • the drain 1 15 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the drain 115 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the drain 1 15 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the drain 1 15 can be deposited using PVD, CVD, MOCVD, and/or ALD.
  • the transistor 101 can include a gate 120.
  • the gate 120 can include a metal.
  • the gate 120 can include a transition metal.
  • the gate 120 can be used to tune the threshold voltage of the device.
  • gate 120 can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate 120 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like.
  • the gate 120 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor 101 can include a gate dielectric 125.
  • the gate dielectric 125 can include a dielectric material.
  • the gate dielectric 125 can include silicon oxide.
  • the gate dielectric 125 can include a high-K dielectric material.
  • the high-K material for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like.
  • an electroglass (EG) can be used as the gate dielectric 125.
  • the gate dielectric 125 can include hydrogenated boron nitride (HBN).
  • the gate material can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate dielectric 125 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • the transistor 101 can include spacers 130 and 135.
  • the spacers 130 and 135 can serve to provide electrical insulation between the gate 120 and the source 110 and/or the drain 115.
  • the spacers 130 and 135 can include silicon oxide or silicon nitride.
  • the spacer can serve to prevent the source 1 10 and/or drain 1 15 from making electrical contact to the gate 120.
  • the spacers 130 and 135 can have a triangle shape.
  • the triangular shape of the spacers 130 and 135 can be due, for example, to an etching step involved in the fabrication of the spacers 130 and 135. That is, the spacers 130 and 135 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 130 and 135 that might remain underneath the source 1 10 and/or drain 115. In one embodiment, the etch can be a directional etch.
  • the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 130 and 135 as well, giving rise to the triangular shape of the spacers 130 and 135.
  • the channel 105 may include a relatively large band gap amorphous oxide semiconductor (for example, an amorphous oxide semiconductor having a band gap on the order of 3 eV or more).
  • this large band gap amorphous oxide semiconductor may result in a relatively high resistance underneath the one or more spacers 130 and 135.
  • the use of a large band gap amorphous oxide semiconductor as the channel 105 may result in a relatively high contact resistance to metal.
  • a high contact resistance to the source 1 10 and/or the drain 115 may result in a relatively large access resistance.
  • FIG. 2A shows a diagram of a partial diagram of a transistor 201, for example, a thin film transistor, in accordance with one or more example embodiments of the disclosure.
  • the transistor 201 can include a substrate 200.
  • the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate 200 can include a silicon substrate.
  • the substrate 200 can include a p-doped silicon substrate.
  • the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • the transistor 201 can include a channel 205.
  • the channel 205 can include an amorphous oxide semiconductor.
  • the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm.
  • the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the drain 225 can include a contact metal.
  • the drain 225 can serve as a Schottky source.
  • the drain 225 can include a nonreactive metal.
  • the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the drain 225 can be deposited using PVD, CVD, and/or ALD.
  • the transistor 201 can include a gate 230.
  • the gate 230 can include a metal.
  • the gate 230 can include a transition metal.
  • the gate 230 can be used to tune the threshold voltage of the device.
  • gate 230 can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor 201 can include a gate dielectric 235.
  • the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • the transistor 201 can include one or more spacers 240 and 245.
  • the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225.
  • the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
  • the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch.
  • FIG. 2B shows a diagram of a transistor 203, for example, a thin film transistor, including oxygen exchange layers, in accordance with one or more example embodiments of the disclosure.
  • oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source and/or drain interface (to be discussed further herein). This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact.
  • the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG. 1).
  • the transistor 201 can include a substrate 200.
  • the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate 200 can include a silicon substrate.
  • the substrate 200 can include a p-doped silicon substrate.
  • the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • the transistor 201 can include a channel 205.
  • the channel 205 can include an amorphous oxide semiconductor.
  • the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the transistor 201 can include a first oxygen exchange layer 210.
  • the first oxygen exchange layer 210 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • the transistor 201 can include a second oxygen exchange layer 215.
  • the second oxygen exchange layer 215 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes.
  • the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • TCN can refer to a trench opening that contacts a diffusion region.
  • a layer of oxide for example, hafnium oxide or an aluminum oxide or a titanium oxide
  • oxide can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
  • the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials
  • the multilayer can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain.
  • the transistor 201 can include a gate 230.
  • the gate 230 can include a metal.
  • the gate 230 can include a transition metal.
  • the gate 230 can be used to tune the threshold voltage of the device.
  • gate 230 can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor 201 can include a gate dielectric 235.
  • the gate dielectric 235 can include a dielectric material.
  • the gate dielectric 235 can include silicon oxide.
  • the gate dielectric 235 can include a high-K dielectric material.
  • the high-K material for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like.
  • an electroglass (EG) can be used as the gate dielectric 235.
  • the gate dielectric 235 can include hexagonal boron nitride (HBN).
  • the gate material can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • the transistor 201 can include one or more spacers 240 and 245.
  • the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source and/or the drain (to be discussed further below).
  • the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can serve to prevent the source and/or drain from making electrical contact to the gate 230.
  • the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source and/or drain (to be discussed further below). In one embodiment, the etch can be a directional etch.
  • the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245.
  • the oxygen exchange layer 210 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source 220 and/or drain 225 interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG. 1).
  • the transistor 201 can include a substrate 200.
  • the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate 200 can include a silicon substrate.
  • the substrate 200 can include a p-doped silicon substrate.
  • the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • the transistor 201 can include a channel 205.
  • the channel 205 can include an amorphous oxide semiconductor.
  • the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm.
  • the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the transistor 201 can include a first oxygen exchange layer 210.
  • the first oxygen exchange layer 210 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • the transistor 201 can include a second oxygen exchange layer 215.
  • the second oxygen exchange layer 215 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes.
  • the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • TCN can refer to a trench opening that contacts a diffusion region.
  • a layer of oxide for example, hafnium oxide or an aluminum oxide or a titanium oxide
  • oxide can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
  • the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials
  • the multilayer can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the transistor 201 can include a source 220. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source and/or drain.
  • the source 220 can include a contact metal.
  • the source 220 can serve as a Schottky source.
  • the source 220 can include a nonreactive metal.
  • the source 220 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the source 220 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the source 220 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the source 220 can be deposited using PVD, CVD, and/or ALD.
  • the transistor 201 can include a drain 225.
  • the drain 225 can include a metal.
  • the drain 225 can include a contact metal.
  • the drain 225 can serve as a Schottky drain.
  • the drain 225 can include a nonreactive metal.
  • a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain. Accordingly, in one embodiment, the drain 225 can include a contact metal.
  • the drain 225 can serve as a Schottky source. In another embodiment, the drain 225 can include a nonreactive metal. In one embodiment, the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the drain 225 can be deposited using PVD, CVD, and/or ALD.
  • the transistor 201 can include a gate 230.
  • the gate 230 can include a metal.
  • the gate 230 can include a transition metal.
  • the gate 230 can be used to tune the threshold voltage of the device.
  • gate 230 can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor 201 can include a gate dielectric 235.
  • the gate dielectric 235 can include a dielectric material.
  • the gate dielectric 235 can include silicon oxide.
  • the gate dielectric 235 can include a high-K dielectric material.
  • the high-K material for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like.
  • an electroglass (EG) can be used as the gate dielectric 235.
  • the gate dielectric 235 can include hexagonal boron nitride (HBN).
  • the gate material can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • the transistor 201 can include one or more spacers 240 and 245.
  • the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225.
  • the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
  • the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch.
  • the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245.
  • the oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • FIG. 2D shows a diagram of a transistor 203, for example, a thin film transistor, including oxygen exchange layers, in accordance with one or more example embodiments of the disclosure.
  • oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source 220 and/or drain 225 interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG.
  • the transistor 201 can include a substrate 200.
  • the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate 200 can include a silicon substrate.
  • the substrate 200 can include a p-doped silicon substrate.
  • the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • a semiconductor material e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • the transistor 201 can include a channel 205.
  • the channel 205 can include an amorphous oxide semiconductor.
  • the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm.
  • the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the transistor 201 can include a first oxygen exchange layer 210.
  • the first oxygen exchange layer 210 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • the transistor 201 can include a second oxygen exchange layer 215.
  • the second oxygen exchange layer 215 can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes.
  • the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • TCN can refer to a trench opening that contacts a diffusion region.
  • a layer of oxide for example, hafnium oxide or an aluminum oxide or a titanium oxide
  • oxide can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
  • the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials
  • the multilayer can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the transistor 201 can include a source 220.
  • a separate source and/or drain from the contacts do not necessarily have to be made.
  • the contacts to the channel can serve as the source and/or drain.
  • the source 220 can include a contact metal.
  • the source 220 can serve as a Schottky source.
  • the source 220 can include a nonreactive metal.
  • the source 220 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the source 220 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the source 220 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the source 220 can be deposited using PVD, CVD, and/or ALD.
  • the transistor 201 can include a drain 225.
  • the drain 225 can include a metal.
  • the drain 225 can include a contact metal.
  • the drain 225 can serve as a Schottky drain.
  • the drain 225 can include a nonreactive metal.
  • the drain 225 can include a contact metal.
  • the drain 225 can serve as a Schottky source.
  • the drain 225 can include a nonreactive metal.
  • the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
  • the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the drain 225 can be deposited using PVD, CVD, and/or ALD.
  • the transistor 201 can include a gate 230.
  • the gate 230 can include a metal.
  • the gate 230 can include a transition metal.
  • the gate 230 can be used to tune the threshold voltage of the device.
  • gate 230 can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor 201 can include a gate dielectric 235.
  • the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • the transistor 201 can include one or more spacers 240 and 245.
  • the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225.
  • the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
  • the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch.
  • the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245.
  • the transistor 201 can include a first depletion layer 250.
  • the first depletion layer 250 may be formed during the operation of the transistor under a voltage bias, for example.
  • the first depletion layer 250 may form undemeath the first oxygen exchange layer 210.
  • the first depletion layer 250 may comprise a depletion region that lacks oxygen.
  • the first depletion layer 250 can have a smaller band gap and be more conductive than the channel 205 comprising the semiconducting oxide.
  • the oxygen exchange layer 210 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the transistor 201 can include a second depletion layer 255.
  • the second depletion layer 255 may be formed during the operation of the transistor under a voltage bias, for example.
  • the second depletion layer 255 may form undemeath the first oxygen exchange layer 210.
  • the second depletion layer 255 may comprise a depletion region that lacks oxygen.
  • the second depletion layer 255 can have a smaller band gap and be more conductive than the channel 205 comprising the semiconducting oxide.
  • the oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • FIG. 3 shows a diagram of an example flowchart for the fabrication of a thin film transistor, in accordance with example embodiments of the disclosure.
  • the steps described below can be performed in any suitable order for the fabrication of the thin film transistor.
  • a substrate can be provided.
  • the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres.
  • the substrate can include a silicon substrate.
  • the substrate can include a p-doped silicon substrate.
  • the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like.
  • the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
  • a channel can be deposited on the substrate.
  • the channel can include an amorphous oxide semiconductor.
  • the channel can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like.
  • the channel may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
  • the channel can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like.
  • the channel can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like.
  • the channel thickness can depend on which technology is used to generate the transistor.
  • the channel can be 4 nm to approximately 50 nm thick, with example thicknesses of approximately 10 nm to approximately 30 nm thick.
  • the channel can be deposited using PVD, CVD, and/or ALD, and the like.
  • a first oxygen exchange layer can be deposited on the channel.
  • the first oxygen exchange layer can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the first oxygen exchange layer can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • a second oxygen exchange layer can be deposited on the channel in a spaced relationship with the first oxygen exchange layer.
  • the second oxygen exchange layer can include a reactive metal.
  • the reactive metal can include a low work function material.
  • the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
  • the second oxygen exchange layer can be deposited using PVD, CVD, and/or ALD, and the like.
  • the first oxygen exchange layer and/or the second oxygen layer may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes.
  • the second oxygen exchange layer can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
  • TCN can refer to a trench opening that contacts a diffusion region.
  • a source can be deposited on the first oxygen exchange layer.
  • a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source and/or drain.
  • the source can include a contact metal.
  • the source can serve as a Schottky source.
  • the source can include a nonreactive metal.
  • the source can include tungsten and/or titanium nitride.
  • the source can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the source can be 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the source can be deposited using PVD, CVD, and/or ALD.
  • a drain can be deposited on the second oxygen exchange layer.
  • the drain can include a metal.
  • the drain can include a contact metal.
  • the drain can serve as a Schottky drain.
  • the drain can include a nonreactive metal.
  • the drain can include tungsten and/or titanium nitride.
  • the drain can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like.
  • the drain can be 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick.
  • the drain can be deposited using PVD, CVD, and/or ALD.
  • a gate dielectric can be provided on the channel.
  • the gate dielectric can include a dielectric material.
  • the gate dielectric can include silicon oxide.
  • the gate dielectric can include a high-K dielectric material.
  • the high-K material for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like.
  • an electroglass (EG) can be used as the gate dielectric.
  • the gate dielectric can include hexagonal boron nitride (HBN).
  • the gate material can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate dielectric can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
  • a gate can be provided on the gate dielectric.
  • the gate can include a metal.
  • the gate can include a transition metal.
  • the gate can be used to tune the threshold voltage of the device.
  • gate can include titanium nitride, cobalt, tungsten and/or platinum.
  • the gate can be deposited using PVD, CVD, and/or ALD, and the like.
  • the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
  • the transistor can include one or more spacers.
  • the spacers can serve to provide electrical insulation between the gate and the source and/or the drain.
  • the spacers can include silicon oxide or silicon nitride. The spacer can serve to prevent the source and/or drain from making electrical contact to the gate.
  • the spacers can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers. That is, the spacers may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers that might remain underneath the source. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers as well, giving rise to the triangular shape of the spacers. [00127] In one embodiment, the transistor can include a first depletion layer.
  • the first depletion layer may be formed during the operation of the transistor under a voltage bias, for example. In another embodiment, the first depletion layer may form underneath the first oxygen exchange layer. In one embodiment, the first depletion layer may comprise a depletion region that lacks oxygen. In one embodiment, the first depletion layer can have a smaller band gap and be more conductive than the channel comprising the semiconducting oxide.
  • the oxygen exchange layer can getter oxygen or perform oxygen exchange with the channel (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the transistor can include a second depletion layer.
  • the second depletion layer may be formed during the operation of the transistor under a voltage bias, for example.
  • the second depletion layer may form underneath the first oxygen exchange layer.
  • the second depletion layer may comprise a depletion region that lacks oxygen.
  • the second depletion layer can have a smaller band gap and be more conductive than the channel comprising the semiconducting oxide.
  • the oxygen exchange layers can getter oxygen or perform oxygen exchange with the channel (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
  • the presence of the oxygen exchange layers can provide oxygen gettering at the source and/or drain interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel. Further, the use of the oxygen exchange layers can reduce the need for doping of the source and/or the drain on the metal contact.
  • FIG. 4 depicts an example of a system 400 according to one or more embodiments of the disclosure.
  • the transistors described in this disclosure can be used in connection with or as a part of any of the components and/or elements described below in connection with system 400.
  • system 400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Intemet appliance or any other type of computing device.
  • system 400 can include a system on a chip (SOC) system.
  • SOC system on a chip
  • system 400 includes multiple processors including processor 410 and processor N 405, where processor N 405 has logic similar or identical to the logic of processor 410.
  • processor 410 has one or more processing cores (represented here by processing core 1 412 and processing core N 412N, where 412N represents the Nth processor core inside processor 410, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 4).
  • processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like.
  • processor 410 has a cache memory 416 to cache instructions and/or data for system 400. Cache memory 416 may be organized into a hierarchical structure including one or more levels of cache memory.
  • processor 410 includes a memory controller (MC) 414, which is configured to perform functions that enable the processor 410 to access and communicate with memory 430 that includes a volatile memory 432 and/or a non-volatile memory 434.
  • processor 410 can be coupled with memory 430 and chipset 420.
  • Processor 410 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals.
  • the wireless antenna 478 operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
  • volatile memory 432 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device.
  • Non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
  • Memory device 430 stores information and instructions to be executed by processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while processor 410 is executing instructions.
  • chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interface 417 and P-P interface 422.
  • PtP Point-to-Point
  • P-P interface 417 and P-P interface 422 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
  • PtP Point-to-Point
  • P-P interface 417 and P-P interface 422 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
  • QPI QuickPath Interconnect
  • chipset 420 can be configured to communicate with processor 410, the processor N 405, display device 440, and other devices 472, 476, 474, 460, 462, 464, 466, 477, etc.
  • Chipset 420 may also be coupled to the wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals.
  • Chipset 420 connects to display device 440 via interface 426.
  • Display 440 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device.
  • processor 410 and chipset 420 are integrated into a single SOC.
  • chipset 420 connects to bus 450 and/or bus 455 that interconnect various elements 474, 460, 462, 464, and 466.
  • Bus 450 and bus 455 may be interconnected via a bus bridge 472.
  • chipset 420 couples with a non-volatile memory 460, a mass storage device(s) 462, a keyboard/mouse 464, and a network interface 466 via interface 424 and/or 404, smart TV 476, consumer electronics 477, etc.
  • mass storage device(s) 462 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium.
  • network interface 466 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a Universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface.
  • the wireless interface operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
  • modules shown in FIG. 4 are depicted as separate blocks within the system 400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits.
  • cache memory 416 is depicted as a separate block within processor 410, cache memory 416 or selected elements thereof can be incorporated into processor core 412.
  • system 400 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc.
  • any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein.
  • microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein.
  • the semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-4), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.
  • the devices may be used in connection with one or more processors.
  • the one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof.
  • the processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks.
  • ASICs application specific integrated circuits
  • ASSPs application specific standard products
  • the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).
  • Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).
  • the devices may be used in connection with one or more additional memory chips.
  • the memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.
  • ROM read-only memory
  • RAM random access memory
  • DRAM dynamic RAM
  • SRAM static RAM
  • SDRAM synchronous dynamic RAM
  • DDR double data rate SDRAM
  • RDRAM RAM-BUS DRAM
  • flash memory devices electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.
  • the electronic device in which the disclosed devices are used and/or provided may be a computing device.
  • a computing device may house one or more boards on which the devices may be disposed.
  • the board may include a number of components including, but not limited to, a processor and/or at least one communication chip.
  • the processor may be physically and electrically connected to the board through, for example, electrical connections of the devices.
  • the computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.
  • the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like.
  • the computing device may be any other electronic device that processes data.
  • Example 1 is a transistor device, comprising: a substrate; a channel disposed on the substrate; a first oxygen exchange layer disposed on the channel; a second oxygen exchange layer disposed on the channel in a spaced relationship with the first oxygen exchange layer; a source disposed on the first oxygen exchange layer; a drain disposed on the second oxygen exchange layer; a gate disposed on the channel between the source and the drain.
  • the device of example 1 can optionally include the channel comprising an amorphous oxide semiconductor.
  • the device of any one of examples 1-2 can optionally include the channel comprising at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide.
  • the device of any one of examples 1-3 can optionally include the substrate comprising silicon, germanium, or a III-V semiconductor.
  • the device of any one of examples 1- 4 can optionally include the oxygen exchange layer comprising a reactive metal.
  • the device of any one of examples 1-5 can optionally include the reactive metal comprising aluminum, hafnium, or titanium.
  • the device of any one of examples 1-6 can optionally include the source comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the device of any one of examples 1-7 can optionally include the drain comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the device of any one of examples 1-8 can optionally include one or more spacers disposed on the channel between the gate and one of the drain or the source.
  • the device of any one of examples 1-9 can optionally include the oxygen exchange layer having a thickness of about 1 nanometer to about 10 nanometers.
  • the device of any one of examples 1-10 can optionally include the channel having a thickness of about 5 nanometers to about 30 nanometers.
  • Example 12 is a method for fabricating a device, the method comprising: providing a substrate; depositing a channel on the substrate; depositing a first oxygen exchange layer on the channel; depositing a second oxygen exchange layer on the channel in a spaced relationship with the first oxygen exchange layer; depositing a source on the first oxygen exchange layer; depositing a drain on the second oxygen exchange layer; depositing a gate on the channel between the source and the drain.
  • the method of example 12 can optionally include annealing at least one of the first oxygen exchange layer or the second oxygen exchange layer.
  • the method of any one of examples 12-13 can optionally include the annealing of the first oxygen exchange layer or the second oxygen exchange layer performed at about 200 degrees centigrade to about 400 degrees centigrade.
  • the method of any one of examples 12-14 can optionally include the annealing of the first oxygen exchange layer or the second oxygen exchange layer performed for a duration of about 15 minutes.
  • the method of any one of examples 12-15 can optionally include the depositing at least one of the channel, the first oxygen exchange layer , the second oxygen exchange layer , the source, the drain, or the gate performed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
  • the method of any one of examples 12-16 can optionally include depositing the channel comprising depositing an amorphous oxide semiconductor.
  • the method of any one of examples 12-17 can optionally include depositing the channel comprising depositing at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide.
  • the method of any one of examples 12-18 can optionally include depositing the substrate comprising depositing depositing at least one of silicon, germanium, or a III-V semiconductor.
  • the method of any one of examples 12-19 can optionally include depositing the oxygen exchange layer comprising depositing a reactive metal.
  • the method of any one of examples 12-20 can optionally include depositing the reactive metal comprising depositing at least one of aluminum, hafnium, or titanium.
  • the method of any one of examples 12-21 can optionally include depositing the drain comprising depositing at least one of a metal, the metal including tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the method of any one of examples 12-22 can optionally include depositing one or more spacers disposed on the channel between the gate and one of the drain or the source.
  • the method of any one of examples 12-23 can optionally include depositing the oxygen exchange layer comprising depositing the oxygen exchange layer having a thickness of about 1 nanometer to aboutlO nanometers.
  • the method of any one of examples 12-24 can optionally include depositing the channel comprising depositing the channel having a thickness of about 5 nanometers to about 30 nanometers.
  • Example 26 is a system comprising: a device, the device comprising: a substrate; a channel disposed on the substrate; a first oxygen exchange layer disposed on the channel; a second oxygen exchange layer disposed on the channel in a spaced relationship with the first oxygen exchange layer; a source disposed on the first oxygen exchange layer; a drain disposed on the second oxygen exchange layer; a gate disposed on the channel between the source and the drain.
  • the system of example 26 can optionally include the channel comprising an amorphous oxide semiconductor.
  • the system of any one of examples 26 or 27 can optionally include the channel comprising at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide.
  • the system of any one of examples 26-28 can optionally include the substrate comprising silicon, germanium, or a III-V semiconductor.
  • the system of any one of examples 26-29 can optionally include the oxygen exchange layer comprising a reactive metal.
  • the system of any one of examples 26-30 can optionally include the reactive metal comprising aluminum, hafnium, or titanium.
  • the system of any one of examples 26-31 can optionally include the source comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the system of any one of examples 26-32 can optionally include the drain comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
  • the system of any one of examples 26-33 can optionally include one or more spacers disposed on the channel between the gate and one of the drain or the source.
  • the system of any one of examples 26-34 can optionally include the oxygen exchange layer having a thickness of about 1 nanometer to about 10 nanometers.
  • the system of any one of examples 26-35 can optionally include the channel having a thickness of about 5 nanometers to about 30 nanometers.

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Abstract

The systems, methods, and apparatus are directed to improving the contact resistance of thin film transistors. The various elements of the transistor that are outside of the gated portion of the transistor can be implicated in increasing the access resistance of the transistor. In one embodiment, oxygen exchange layers can be used between the source and/or drain (or contacts for thin film transistors) and the channel of the transistor. In one embodiment, oxygen exchange layers can include reactive metals having a relatively low work function and can include aluminum, titanium, hafnium, zirconium, and the like. In one embodiment, the use of reactive metals between the source and/or drain (or contacts for thin film transistors) can thereby reduce the contact resistance to the channel of the transistor.

Description

TRANSISTORS WITH OXYGEN EXCHANGE LAYERS IN THE SOURCE AND
DRAIN
TECHNICAL FIELD
[0001] This disclosure generally relates to transistors. BACKGROUND
[0002] Metal-oxide semiconductor field-effect transistors (MOSFETs) can represent transistor devices can be used for logic and memory. It may be desirable to have a transistor device that turns on at a current level that is significantly higher than a current level at which the transistor device turns off. A transistor device having a high on to off current ratio can have be faster and use lower power (for example, lower standby power) than a transistor device having a lower on to off current ratio. Such transistor devices (for example, MOSFET devices) may need to be fabricated in silicon using high temperature processing, for example, in order to gate the source and the drain of the transistor device.
BRIEF DESCRIPTION OF THE FIGURES [0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
[0004] FIG. 1 shows a diagram of a thin film transistor, having at least a source, a drain, and a gate.
[0005] FIG. 2A shows a diagram of a partial structure of a thin film transistor, in accordance with one or more example embodiments of the disclosure.
[0006] FIG. 2B shows a diagram of another partial structure of a thin film transistor, having oxygen exchange layers, in accordance with one or more example embodiments of the disclosure.
[0007] FIG. 2C shows a diagram of another partial structure of a thin film transistor having a source and a drain, in accordance with one or more example embodiments of the disclosure. [0008] FIG. 2D shows a diagram of another partial structure of a thin film transistor having depletion layers, in accordance with one or more example embodiments of the disclosure.
[0009] FIG. 3 shows an example flowchart for the fabrication of a thin film transistor, in accordance with example embodiments of the disclosure.
[0010] FIG. 4 shows a diagram of an example system, in accordance with example embodiments of the disclosure.
DETAILED DESCRIPTION
[0011] Embodiments of the disclosure are described more fully herein after with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.
[0012] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.
[0013] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.
[0014] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to a horizontal plane, where the horizontal plane can include an x- y plane, a x-z plane, or a y-z plane, as the case may be. The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.
[0015] In one embodiment, disclosed herein are systems, methods, and apparatus directed to thin film transistors. In one embodiment, such thin film transistors can include metal-oxide semiconductor field-effect transistors (MOSFETs). In one embodiment, the thin film transistors can be fabricated on a silicon substrate. Alternatively or additionally, in an embodiment, the thin film transistors can be made in a semiconducting material, such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. [0016] In one embodiment, the thin film transistor may need to comply with low temperature processing, such as low temperature processing used in backend-of-line (BEOL) processing. In one embodiment, BEOL processing can refer to a portion of Integrated circuit (IC) fabrication, where individual devices (transistors, capacitors, resistors, and the like) are interconnected with wiring on a wafer. In one embodiment, the thin film transistor may need to comply with low temperature processing for compatibility with existing logic and memory devices in silicon. For example, functionality can be added to existing logic and memory devices in silicon by adding these extra transistors in different metal layers or in the BEOL processing.
[0017] In one embodiment, front-end-of-line (FEOL) processing methods can refer to methods for the formation of transistors directly in silicon. In one embodiment, in BEOL processing, the processing may need to be performed at relatively lower temperatures, for example, less than 450 degrees centigrade. Thin film transistors made at such lower temperatures may need to meet predetermined contact resistance and gating properties without the use of high temperature processing, as in FEOL processing. In one embodiment, the use of high temperature annealing can be used to heal and make transistors more efficient. In one embodiment, high temperature processing can crystallize silicon, activate dopants in various regions of the transistor, and/or heal damage in the gate dielectric of a transistor.
[0018] In one embodiment thin film transistors, may need to be deposited at low temperatures on a non-native substrate (that is, a substrate that comprises a material that cannot withstand high temperature processing steps). Such thin film transistors may nevertheless need to have high device on to off ratios. One challenge in the fabrication of low temperature devices can involve achieving suitable contacts. For FEOL processing, a high dopant concentration in the source and drain of a transistor can permit an increase in the level of current flowing in transistor during operation. However, in one embodiment, devices fabricated using BEOL processing may not have the option to be implanted with dopants or otherwise have impurities (for example, phosphorous or boron impurities) that can be annealed at high temperatures and thereby activated.
[0019] In one embodiment, the systems, methods, and apparatus are directed to improving the contact resistance associated with thin film transistors. In one embodiment, the disclosure can permit gating of the semiconducting material from low off current levels to high on current levels. In one embodiment, a high on current in the transistor can be limited, in part, by the access resistance, or external resistance to the channel of the transistor. In one embodiment, one or more elements of the transistor that are outside of the gated portion of the transistor can be implicated in increasing the access resistance.
[0020] In one embodiment, the channel of the transistor can include thin film transistor material, which can be a semiconducting oxide. In one embodiment, the semiconducting oxide can include an amorphous semiconducting oxide that can be deposited at low temperature. In one embodiment, the thin film transistor material can include a semiconducting oxide that can be indium gallium zinc oxide (IGZO). In one embodiment, IGZO can have a relatively wide band gap relative to silicon. In one embodiment, the band gap of silicon can be approximately 1.1 electron volts (eV), while the bandgap of IGZO can be approximately 3 eV.
[0021] In one embodiment, contacting a channel comprising a semiconducting oxide with a wide band gap (such as IGZO) may involve overcoming an energy barrier that may otherwise prevent the injection of carriers into the semiconducting oxide. In another embodiment, for channels including a thin film transistor material such as a semiconducting oxide having a larger band gap, it can become harder to achieve a low contact resistance to the channel of the transistor. A low resistance contact to small band gap semiconductors like, for example, Indium Arsenide (having a band gap of approximately 0.36 eV), can be relatively straightforward with conventional semiconductor processing techniques. For higher bandgaps, for example, bandgaps on the order of 1 eV (for example, for silicon), and/or 3 eV, (for example, for IGZO), the contact resistance can increase. For materials having even higher bandgaps (for example, band gap larger than approximately 5 eV), the material may generally serve as an insulator, and the contact resistance can increase further. For materials having such high bandgaps, the current flow through the material can be negligible. For comparison, a metal may not have a band gap, thereby the metal can have many carriers.
[0022] In one embodiment, many thin film semiconducting oxides can include multi-metal systems (for example, indium, gallium, zinc, and the like) and an oxide. In one embodiment, the systems, methods, and apparatus disclosed herein describe reducing the oxide component of the semiconducting oxides comprising the channel of the transistor in order to make the semiconducting oxides more metallic. As such, the semiconducting oxides can have a narrower band gap and have more carriers; further the contact resistance to the semiconducting oxides will be exponentially reduced. [0023] In one embodiment, reactive metals can be used between the source and/or drain (or contacts, as the case may be) and the channel of the transistor. In one embodiment, reactive metals can include metals having a relatively low work function. In one embodiment, reactive metals can include aluminum, titanium, hafnium, zirconium, and the like. In one embodiment, such reactive metals may bond to oxygen and nitrogen or other elements to become more stable. [0024] In one embodiment, the reactive metal can be deposited beneath the source and/or drain region of the transistor before depositing the metal contact to the semiconducting oxide (for example, the IGZO) serving as the channel to the transistor. In one embodiment, the reactive metal can serve as an oxygen exchange layer. That is, the reactive metal can remove oxygen from the semiconducting oxide. It can pull oxygen out of semiconducting oxide (for example, the IGZO) thin film material and it can make the semiconducting oxide become more metallic and more conductive. Accordingly, the contact resistance to the semiconducting oxide can be reduced. With less oxygen, the semiconducting oxide can become more metallic, can have more charge, and higher mobility. It can result in lower source drain resistance, lower contact resistance, than the thin film transistor without this reactive metal in the contact.
[0025] In one embodiment, because of the oxygen exchange layer removing the oxygen out of the semiconducting oxide layer of the channel, the band gap can be reduced (for example, in the case of a channel comprising a semiconductor oxide layer of IGZO having a bandgap of approximately 3.2 eV, the bandgap of the channel comprising the semiconducting oxide having oxygen removed can be reduced to less than approximately 2 eV). The reduction in the bandgap in the semiconducting oxide can allow more carriers to exist in the channel comprising semiconducting oxide having oxygen removed. The reduced bandgap, increased carrier concentration, and the increased mobility can result in a reduced contact resistance and improved transistor performance.
[0026] FIG. 1 shows a diagram of an example transistor, for example, a thin film transistor 101 in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 101 can include a substrate 100. In one embodiment, the substrate 100 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 100 can include a silicon substrate. In one embodiment, the substrate 100 can include a p-doped silicon substrate. In one embodiment, the substrate 100 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 100 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). [0027] In another embodiment, the transistor 101 can include a channel. In one embodiment, the channel 105 can include an amorphous oxide semiconductor. In another embodiment, the channel 105 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 105 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[0028] In one embodiment, the channel 105 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 105 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
[0029] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 105 can be approximately 4 nm to approximately 50 nm thick, with example thicknesses of approximately 10 nm to approximately 30 nm thick. In one embodiment, the channel 105 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.
[0030] In one embodiment, the transistor 101 can include a source 110. In another embodiment, the source 110 can include a metal. In one embodiment, for transistors having a channel 105 comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 105 can serve as the source 110 and/or drain 115 (to be discussed further below). Accordingly, in one embodiment, the source 110 can include a contact metal. In one embodiment, the source 110 can serve as a Schottky source. In another embodiment, the source 110 can include a nonreactive metal. In one embodiment, the source 110 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
[0031] In another embodiment, the source 110 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the source 110 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the source 1 10 can be deposited using PVD, CVD, MOCVD, and/or ALD.
[0032] In one embodiment, the transistor 101 can include a drain 1 15. In another embodiment, the drain 115 can include a metal. In one embodiment, the drain 1 15 can include a contact metal. In one embodiment, the drain 115 can serve as a Schottky drain. In another embodiment, the drain 1 15 can include a nonreactive metal. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source 110 and/or drain 115. In one embodiment, the drain 1 15 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. In another embodiment, the drain 115 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the drain 1 15 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the drain 1 15 can be deposited using PVD, CVD, MOCVD, and/or ALD.
[0033] In one embodiment, the transistor 101 can include a gate 120. In another embodiment, the gate 120 can include a metal. In another embodiment, the gate 120 can include a transition metal. In one embodiment, the gate 120 can be used to tune the threshold voltage of the device. In one embodiment, gate 120 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 120 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In one embodiment, the gate 120 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
[0034] In another embodiment, the transistor 101 can include a gate dielectric 125. In one embodiment, the gate dielectric 125 can include a dielectric material. In another embodiment, the gate dielectric 125 can include silicon oxide. In another embodiment, the gate dielectric 125 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 125. In one embodiment, the gate dielectric 125 can include hydrogenated boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 125 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
[0035] In one embodiment, the transistor 101 can include spacers 130 and 135. In an embodiment, the spacers 130 and 135 can serve to provide electrical insulation between the gate 120 and the source 110 and/or the drain 115. In one embodiment, the spacers 130 and 135 can include silicon oxide or silicon nitride. In one embodiment, the spacer can serve to prevent the source 1 10 and/or drain 1 15 from making electrical contact to the gate 120.
[0036] In one embodiment, the spacers 130 and 135 can have a triangle shape. In another embodiment, the triangular shape of the spacers 130 and 135 can be due, for example, to an etching step involved in the fabrication of the spacers 130 and 135. That is, the spacers 130 and 135 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 130 and 135 that might remain underneath the source 1 10 and/or drain 115. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 130 and 135 as well, giving rise to the triangular shape of the spacers 130 and 135.
[0037] In an embodiment, the channel 105 may include a relatively large band gap amorphous oxide semiconductor (for example, an amorphous oxide semiconductor having a band gap on the order of 3 eV or more). In another embodiment, this large band gap amorphous oxide semiconductor may result in a relatively high resistance underneath the one or more spacers 130 and 135.
[0038] In another embodiment, the use of a large band gap amorphous oxide semiconductor as the channel 105 may result in a relatively high contact resistance to metal. For example, a high contact resistance to the source 1 10 and/or the drain 115. Finally, in another embodiment, the use of a large band gap amorphous oxide semiconductor as the channel 105 may result in a relatively large access resistance.
[0039] FIG. 2A shows a diagram of a partial diagram of a transistor 201, for example, a thin film transistor, in accordance with one or more example embodiments of the disclosure. In one embodiment, the transistor 201 can include a substrate 200. In one embodiment, the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 200 can include a silicon substrate. In one embodiment, the substrate 200 can include a p-doped silicon substrate. In one embodiment, the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). [0040] In one embodiment, the transistor 201 can include a channel 205. In one embodiment, the channel 205 can include an amorphous oxide semiconductor. In another embodiment, the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[0041] In one embodiment, the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like.
[0042] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
[0043] In one embodiment, for transistors having a channel 205 comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain. Accordingly, in one embodiment, the drain 225 can include a contact metal. In one embodiment, the drain 225 can serve as a Schottky source. In another embodiment, the drain 225 can include a nonreactive metal. In one embodiment, the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
[0044] In another embodiment, the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the drain 225 can be deposited using PVD, CVD, and/or ALD.
[0045] In one embodiment, the transistor 201 can include a gate 230. In another embodiment, the gate 230 can include a metal. In another embodiment, the gate 230 can include a transition metal. In one embodiment, the gate 230 can be used to tune the threshold voltage of the device. In one embodiment, gate 230 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. [0046] In one embodiment, the transistor 201 can include a gate dielectric 235. In one embodiment, the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
[0047] In one embodiment, the transistor 201 can include one or more spacers 240 and 245. In an embodiment, the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225. In one embodiment, the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
[0048] In one embodiment, the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245. [0049] FIG. 2B shows a diagram of a transistor 203, for example, a thin film transistor, including oxygen exchange layers, in accordance with one or more example embodiments of the disclosure. In one embodiment, oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0050] In various embodiments, the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source and/or drain interface (to be discussed further herein). This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG. 1). [0051] In one embodiment, the transistor 201 can include a substrate 200. In one embodiment, the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 200 can include a silicon substrate. In one embodiment, the substrate 200 can include a p-doped silicon substrate. In one embodiment, the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). [0052] In one embodiment, the transistor 201 can include a channel 205. In one embodiment, the channel 205 can include an amorphous oxide semiconductor. In another embodiment, the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[0053] In one embodiment, the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. [0054] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
[0055] In one embodiment, the transistor 201 can include a first oxygen exchange layer 210. In another embodiment, the first oxygen exchange layer 210 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
[0056] In one embodiment, the transistor 201 can include a second oxygen exchange layer 215. In another embodiment, the second oxygen exchange layer 215 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like. [0057] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes. In one embodiment, the more the reactive metal is heated the more it can drive a reaction for the first oxygen exchange layer 210 to getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0058] In one embodiment, the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm. In one embodiment, the too thick to fill up a TCN. As used herein, TCN can refer to a trench opening that contacts a diffusion region. In one embodiment, it may be necessary to etch a TCN comprising a hole in order to make a contact, and the hole may have oxide on the edge. Accordingly, just as the oxygen exchange layer comprising a reactive metal can remove oxygen from the channel comprising semiconducting oxide, the oxygen exchange layer comprising a reactive metal can remove oxygen from the isolation. Further, since there can be a large source of oxygen from the isolation, a layer of oxide (for example, hafnium oxide or an aluminum oxide or a titanium oxide) can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
[0059] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials In one embodiment, the multilayer can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
[0060] In one embodiment, for transistors having a channel 205 comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain.
[0061] In one embodiment, the transistor 201 can include a gate 230. In another embodiment, the gate 230 can include a metal. In another embodiment, the gate 230 can include a transition metal. In one embodiment, the gate 230 can be used to tune the threshold voltage of the device. In one embodiment, gate 230 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
[0062] In one embodiment, the transistor 201 can include a gate dielectric 235. In one embodiment, the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. [0063] In one embodiment, the transistor 201 can include one or more spacers 240 and 245. In an embodiment, the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source and/or the drain (to be discussed further below). In one embodiment, the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can serve to prevent the source and/or drain from making electrical contact to the gate 230.
[0064] In one embodiment, the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source and/or drain (to be discussed further below). In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245. [0065] In one embodiment, the oxygen exchange layer 210 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal. [0066] FIG. 2C shows a diagram of a transistor 203, for example, a thin film transistor, including oxygen exchange layers and source and drain layers, in accordance with one or more example embodiments of the disclosure. In one embodiment, oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0067] In various embodiments, the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source 220 and/or drain 225 interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG. 1).
[0068] In one embodiment, the transistor 201 can include a substrate 200. In one embodiment, the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 200 can include a silicon substrate. In one embodiment, the substrate 200 can include a p-doped silicon substrate. In one embodiment, the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof). [0069] In one embodiment, the transistor 201 can include a channel 205. In one embodiment, the channel 205 can include an amorphous oxide semiconductor. In another embodiment, the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[0070] In one embodiment, the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
[0071] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
[0072] In one embodiment, the transistor 201 can include a first oxygen exchange layer 210. In another embodiment, the first oxygen exchange layer 210 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
[0073] In one embodiment, the transistor 201 can include a second oxygen exchange layer 215. In another embodiment, the second oxygen exchange layer 215 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like.
[0074] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes. In one embodiment, the more the reactive metal is heated the more it can drive a reaction for the first oxygen exchange layer 210 to getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0075] In one embodiment, the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm. In one embodiment, the too thick to fill up a TCN. As used herein, TCN can refer to a trench opening that contacts a diffusion region. In one embodiment, it may be necessary to etch a TCN comprising a hole in order to make a contact, and the hole may have oxide on the edge. Accordingly, just as the oxygen exchange layer comprising a reactive metal can remove oxygen from the channel comprising semiconducting oxide, the oxygen exchange layer comprising a reactive metal can remove oxygen from the isolation. Further, since there can be a large source of oxygen from the isolation, a layer of oxide (for example, hafnium oxide or an aluminum oxide or a titanium oxide) can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
[0076] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials In one embodiment, the multilayer can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. [0077] In one embodiment, the transistor 201 can include a source 220. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source and/or drain. Accordingly, in one embodiment, the source 220 can include a contact metal. In one embodiment, the source 220 can serve as a Schottky source. In another embodiment, the source 220 can include a nonreactive metal. In one embodiment, the source 220 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel. [0078] In another embodiment, the source 220 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the source 220 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the source 220 can be deposited using PVD, CVD, and/or ALD.
[0079] In one embodiment, the transistor 201 can include a drain 225. In another embodiment, the drain 225 can include a metal. In one embodiment, the drain 225 can include a contact metal. In one embodiment, the drain 225 can serve as a Schottky drain. In another embodiment, the drain 225 can include a nonreactive metal. [0080] In one embodiment, for transistors having a channel 205 comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain. Accordingly, in one embodiment, the drain 225 can include a contact metal. In one embodiment, the drain 225 can serve as a Schottky source. In another embodiment, the drain 225 can include a nonreactive metal. In one embodiment, the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
[0081] In another embodiment, the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the drain 225 can be deposited using PVD, CVD, and/or ALD.
[0082] In one embodiment, the transistor 201 can include a gate 230. In another embodiment, the gate 230 can include a metal. In another embodiment, the gate 230 can include a transition metal. In one embodiment, the gate 230 can be used to tune the threshold voltage of the device. In one embodiment, gate 230 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
[0083] In one embodiment, the transistor 201 can include a gate dielectric 235. In one embodiment, the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
[0084] In one embodiment, the transistor 201 can include one or more spacers 240 and 245. In an embodiment, the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225. In one embodiment, the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
[0085] In one embodiment, the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245.
[0086] In one embodiment, the oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0087] FIG. 2D shows a diagram of a transistor 203, for example, a thin film transistor, including oxygen exchange layers, in accordance with one or more example embodiments of the disclosure. In one embodiment, oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with a channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0088] In various embodiments, the presence of the oxygen exchange layers 210 and/or 215 can provide oxygen gettering at the source 220 and/or drain 225 interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers 210 and 215 can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel underneath the gate. Further, the use of the oxygen exchange layers 210 and 215 can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers 210 and 215 can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers 210 and 215 (for example, the transistor 101 shown and described in connection with FIG.
1). [0089] In one embodiment, the transistor 201 can include a substrate 200. In one embodiment, the substrate 200 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 200 can include a silicon substrate. In one embodiment, the substrate 200 can include a p-doped silicon substrate. In one embodiment, the substrate 200 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 200 can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III- V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
[0090] In one embodiment, the transistor 201 can include a channel 205. In one embodiment, the channel 205 can include an amorphous oxide semiconductor. In another embodiment, the channel 205 can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel 205 may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[0091] In one embodiment, the channel 205 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel 205 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), poly crystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like.
[0092] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel 205 can be approximately 3 nm to approximately 50 nm thick, with example thicknesses of approximately 5 nm to approximately 20 nm. In one embodiment, the channel 205 can be deposited using PVD, CVD, and/or ALD, and the like.
[0093] In one embodiment, the transistor 201 can include a first oxygen exchange layer 210. In another embodiment, the first oxygen exchange layer 210 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the first oxygen exchange layer 210 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the first oxygen exchange layer 210 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
[0094] In one embodiment, the transistor 201 can include a second oxygen exchange layer 215. In another embodiment, the second oxygen exchange layer 215 can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the second oxygen exchange layer 215 can be deposited using PVD, CVD, and/or ALD, and the like.
[0095] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen layer 215 may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes. In one embodiment, the more the reactive metal is heated the more it can drive a reaction for the first oxygen exchange layer 210 to getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[0096] In one embodiment, the second oxygen exchange layer 215 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm. In one embodiment, the too thick to fill up a TCN. As used herein, TCN can refer to a trench opening that contacts a diffusion region. In one embodiment, it may be necessary to etch a TCN comprising a hole in order to make a contact, and the hole may have oxide on the edge. Accordingly, just as the oxygen exchange layer comprising a reactive metal can remove oxygen from the channel comprising semiconducting oxide, the oxygen exchange layer comprising a reactive metal can remove oxygen from the isolation. Further, since there can be a large source of oxygen from the isolation, a layer of oxide (for example, hafnium oxide or an aluminum oxide or a titanium oxide) can form, which can be insulating. This can result in the contact hole of the TCN becoming small and lead to a bad contact resistance.
[0097] In one embodiment, the first oxygen exchange layer 210 and/or the second oxygen exchange layer 215 can include a multilayer comprising one or more layers of suitable materials In one embodiment, the multilayer can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like.
[0098] In one embodiment, the transistor 201 can include a source 220. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made.
That is, for example, the contacts to the channel can serve as the source and/or drain.
Accordingly, in one embodiment, the source 220 can include a contact metal. In one embodiment, the source 220 can serve as a Schottky source. In another embodiment, the source 220 can include a nonreactive metal. In one embodiment, the source 220 can include tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
[0099] In another embodiment, the source 220 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the source 220 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the source 220 can be deposited using PVD, CVD, and/or ALD.
[00100] In one embodiment, the transistor 201 can include a drain 225. In another embodiment, the drain 225 can include a metal. In one embodiment, the drain 225 can include a contact metal. In one embodiment, the drain 225 can serve as a Schottky drain. In another embodiment, the drain 225 can include a nonreactive metal.
[00101] In one embodiment, for transistors having a channel 205 comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel 205 can serve as the source and/or drain. Accordingly, in one embodiment, the drain 225 can include a contact metal. In one embodiment, the drain 225 can serve as a Schottky source. In another embodiment, the drain 225 can include a nonreactive metal. In one embodiment, the drain 225 can include tungsten and/or titanium nitride, aluminum, titanium, tantalum nitride, cobalt, and/or nickel.
[00102] In another embodiment, the drain 225 can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the drain 225 can be approximately 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the drain 225 can be deposited using PVD, CVD, and/or ALD.
[00103] In one embodiment, the transistor 201 can include a gate 230. In another embodiment, the gate 230 can include a metal. In another embodiment, the gate 230 can include a transition metal. In one embodiment, the gate 230 can be used to tune the threshold voltage of the device. In one embodiment, gate 230 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 230 can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate 230 can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm. [00104] In one embodiment, the transistor 201 can include a gate dielectric 235. In one embodiment, the gate dielectric 235 can include a dielectric material. In another embodiment, the gate dielectric 235 can include silicon oxide. In another embodiment, the gate dielectric 235 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric 235. In one embodiment, the gate dielectric 235 can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric 235 can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm. [00105] In one embodiment, the transistor 201 can include one or more spacers 240 and 245. In an embodiment, the spacers 240 and 245 can serve to provide electrical insulation between the gate 230 and the source 220 and/or the drain 225. In one embodiment, the spacers 240 and 245 can include silicon oxide or silicon nitride. The spacer can be serve to prevent the source 220 and/or drain 225 from making electrical contact to the gate 230.
[00106] In one embodiment, the spacers 240 and 245 can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers 240 and 245. That is, the spacers 240 and 245 may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers 240 and 245 that might remain underneath the source 220 and/or drain 225. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers 240 and 245 as well, giving rise to the triangular shape of the spacers 240 and 245. [00107] In one embodiment, the transistor 201 can include a first depletion layer 250. In another embodiment, the first depletion layer 250 may be formed during the operation of the transistor under a voltage bias, for example. In another embodiment, the first depletion layer 250 may form undemeath the first oxygen exchange layer 210. In one embodiment, the first depletion layer 250 may comprise a depletion region that lacks oxygen. In one embodiment, the first depletion layer 250 can have a smaller band gap and be more conductive than the channel 205 comprising the semiconducting oxide.
[00108] In one embodiment, the oxygen exchange layer 210 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[00109] In one embodiment, the transistor 201 can include a second depletion layer 255. In another embodiment, the second depletion layer 255 may be formed during the operation of the transistor under a voltage bias, for example. In another embodiment, the second depletion layer 255 may form undemeath the first oxygen exchange layer 210. In one embodiment, the second depletion layer 255 may comprise a depletion region that lacks oxygen. In one embodiment, the second depletion layer 255 can have a smaller band gap and be more conductive than the channel 205 comprising the semiconducting oxide.
[00110] In one embodiment, the oxygen exchange layers 210 and/or 215 can getter oxygen or perform oxygen exchange with the channel 205 (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[00111] FIG. 3 shows a diagram of an example flowchart for the fabrication of a thin film transistor, in accordance with example embodiments of the disclosure. In one embodiment, the steps described below can be performed in any suitable order for the fabrication of the thin film transistor. In block 302, a substrate can be provided. In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a p-doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (e.g., monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (e.g., gallium arsenide, GaAs), or any combination thereof).
[00112] In block 304, a channel can be deposited on the substrate. In one embodiment, the channel can include an amorphous oxide semiconductor. In another embodiment, the channel can include a zinc oxide (ZnO), an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO) or an antimony oxide material and/or the like. In one embodiment, the channel may include a material that has a wide-band gap with respect to silicon (approximately 1.1 eV).
[00113] In one embodiment, the channel can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the channel can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like.
[00114] In one embodiment, the channel thickness can depend on which technology is used to generate the transistor. In another embodiment, the channel can be 4 nm to approximately 50 nm thick, with example thicknesses of approximately 10 nm to approximately 30 nm thick. In one embodiment, the channel can be deposited using PVD, CVD, and/or ALD, and the like.
[00115] In block 306, a first oxygen exchange layer can be deposited on the channel. In another embodiment, the first oxygen exchange layer can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the first oxygen exchange layer can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the first oxygen exchange layer can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm.
[00116] In block 308, a second oxygen exchange layer can be deposited on the channel in a spaced relationship with the first oxygen exchange layer. In another embodiment, the second oxygen exchange layer can include a reactive metal. In one embodiment, the reactive metal can include a low work function material. In one embodiment, the reactive metal can include aluminum, hafnium, titanium, zirconium, and the like. In one embodiment, the second oxygen exchange layer can be deposited using PVD, CVD, and/or ALD, and the like.
[00117] In one embodiment, the first oxygen exchange layer and/or the second oxygen layer may be annealed at approximately 200° C to approximately 400° C from about 1 second to about 30 minutes with preferential ranges between 1 second and 15 minutes. In one embodiment, the more the reactive metal is heated the more it will drive the reaction for the first oxygen exchange layer to getter oxygen or perform oxygen exchange with the channel (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[00118] In one embodiment, the second oxygen exchange layer can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 3 nm to approximately 6 nm. In one embodiment, the too thick to fill up a TCN. As used herein, TCN can refer to a trench opening that contacts a diffusion region. In one embodiment, it may be necessary to etch a TCN comprising a hole in order to make a contact, and the hole may have oxide on the edge. Accordingly, just as the oxygen exchange layer comprising a reactive metal can remove oxygen from the channel comprising semiconducting oxide, the oxygen exchange layer comprising a reactive metal can remove oxygen from the isolation. Further, since there can be a large source of oxygen from the isolation, a layer of oxide (for example, hafnium oxide or an aluminum oxide or a titanium oxide) can form, which can be insulating. This can result in the contact hole of the TCN become small and lead to a bad contact resistance. [00119] In block 310, a source can be deposited on the first oxygen exchange layer. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source and/or drain. Accordingly, in one embodiment, the source can include a contact metal. In one embodiment, the source can serve as a Schottky source. In another embodiment, the source can include a nonreactive metal. In one embodiment, the source can include tungsten and/or titanium nitride.
[00120] In another embodiment, the source can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the source can be 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the source can be deposited using PVD, CVD, and/or ALD.
[00121] In block 312, a drain can be deposited on the second oxygen exchange layer. In another embodiment, the drain can include a metal. In one embodiment, the drain can include a contact metal. In one embodiment, the drain can serve as a Schottky drain. In another embodiment, the drain can include a nonreactive metal. In one embodiment, for transistors having a channel comprising a thin film semiconducting oxide, a separate source and/or drain from the contacts do not necessarily have to be made. That is, for example, the contacts to the channel can serve as the source and/or drain. Accordingly, in one embodiment, the drain can include a contact metal. In one embodiment, the drain can serve as a Schottky source. In another embodiment, the drain can include a nonreactive metal. In one embodiment, the drain can include tungsten and/or titanium nitride.
[00122] In another embodiment, the drain can include doped or undoped black phosphorous, titanium, tantalum, cobalt, molybdenum, tantalum nitride, hafnium, copper, gadolinium, and the like. In another embodiment, the drain can be 10 nanometer to approximately 80 nm thick, with example thicknesses of approximately 10 nm to approximately 40 nm thick. In one embodiment, the drain can be deposited using PVD, CVD, and/or ALD.
[00123] In block 314, a gate dielectric can be provided on the channel. In one embodiment, the gate dielectric can include a dielectric material. In another embodiment, the gate dielectric can include silicon oxide. In another embodiment, the gate dielectric can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In one embodiment, an electroglass (EG) can be used as the gate dielectric. In one embodiment, the gate dielectric can include hexagonal boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate dielectric can have a thickness of approximately 1 nm to approximately 10 nm, with an example thickness of approximately 2 nm to approximately 4 nm.
[00124] In block 316, a gate can be provided on the gate dielectric. In another embodiment, the gate can include a metal. In another embodiment, the gate can include a transition metal. In one embodiment, the gate can be used to tune the threshold voltage of the device. In one embodiment, gate can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate can be deposited using PVD, CVD, and/or ALD, and the like. In one embodiment, the gate can have a thickness of approximately 30 nm to approximately 100 nm, with an example thickness of approximately 40 nm to approximately 60 nm.
[00125] In one embodiment, the transistor can include one or more spacers. In an embodiment, the spacers can serve to provide electrical insulation between the gate and the source and/or the drain. In one embodiment, the spacers can include silicon oxide or silicon nitride. The spacer can serve to prevent the source and/or drain from making electrical contact to the gate.
[00126] In one embodiment, the spacers can have a triangle shape. This can be due, for example, to an etching step involved in the fabrication of the spacers. That is, the spacers may be first deposited as a blanket layer, and then an etch can be used to remove a portion of the insulating spacers that might remain underneath the source. In one embodiment, the etch can be a directional etch. In another embodiment, the etch may not etch straight downward (in the negative z direction); rather, the etch may have a slight slant and etch more of the top of the spacers as well, giving rise to the triangular shape of the spacers. [00127] In one embodiment, the transistor can include a first depletion layer. In another embodiment, the first depletion layer may be formed during the operation of the transistor under a voltage bias, for example. In another embodiment, the first depletion layer may form underneath the first oxygen exchange layer. In one embodiment, the first depletion layer may comprise a depletion region that lacks oxygen. In one embodiment, the first depletion layer can have a smaller band gap and be more conductive than the channel comprising the semiconducting oxide.
[00128] In one embodiment, the oxygen exchange layer can getter oxygen or perform oxygen exchange with the channel (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[00129] In one embodiment, the transistor can include a second depletion layer. In another embodiment, the second depletion layer may be formed during the operation of the transistor under a voltage bias, for example. In another embodiment, the second depletion layer may form underneath the first oxygen exchange layer. In one embodiment, the second depletion layer may comprise a depletion region that lacks oxygen. In one embodiment, the second depletion layer can have a smaller band gap and be more conductive than the channel comprising the semiconducting oxide.
[00130] In one embodiment, the oxygen exchange layers can getter oxygen or perform oxygen exchange with the channel (for example, perform oxygen exchange with an amorphous oxide semiconductor comprising the channel), thereby, increasing charge mobility, decreasing band gap and decreasing contact resistance without the need for high temperature or implant anneal.
[00131] In various embodiments, the presence of the oxygen exchange layers can provide oxygen gettering at the source and/or drain interface. This can lead, among other factors, to more oxygen vacancies in the channel (for example, the channel comprising an amorphous oxide semiconductor), therefore, a higher conductivity and a lower contact resistance. Additionally, the use of the oxygen exchange layers can variously lead to the maintenance of a low leakage current and/or a better gating property of wide-band gap amorphous oxide semiconductors in the channel. Further, the use of the oxygen exchange layers can reduce the need for doping of the source and/or the drain on the metal contact. In another embodiment, the use of the oxygen exchange layers can result in a lower total access resistance TFT with respect to transistors not having the oxygen exchange layers (for example, the transistor 101 shown and described in connection with FIG. 1). [00132] FIG. 4 depicts an example of a system 400 according to one or more embodiments of the disclosure. In one embodiment, the transistors described in this disclosure can be used in connection with or as a part of any of the components and/or elements described below in connection with system 400. In one embodiment, system 400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Intemet appliance or any other type of computing device. In some embodiments, system 400 can include a system on a chip (SOC) system.
[00133] In one embodiment, system 400 includes multiple processors including processor 410 and processor N 405, where processor N 405 has logic similar or identical to the logic of processor 410. In one embodiment, processor 410 has one or more processing cores (represented here by processing core 1 412 and processing core N 412N, where 412N represents the Nth processor core inside processor 410, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 4). In some embodiments, processing core 412 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 410 has a cache memory 416 to cache instructions and/or data for system 400. Cache memory 416 may be organized into a hierarchical structure including one or more levels of cache memory.
[00134] In some embodiments, processor 410 includes a memory controller (MC) 414, which is configured to perform functions that enable the processor 410 to access and communicate with memory 430 that includes a volatile memory 432 and/or a non-volatile memory 434. In some embodiments, processor 410 can be coupled with memory 430 and chipset 420. Processor 410 may also be coupled to a wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 478 operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [00135] In some embodiments, volatile memory 432 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
[00136] Memory device 430 stores information and instructions to be executed by processor 410. In one embodiment, memory 430 may also store temporary variables or other intermediate information while processor 410 is executing instructions. In the illustrated embodiment, chipset 420 connects with processor 410 via Point-to-Point (PtP or P-P) interface 417 and P-P interface 422. Chipset 420 enables processor 410 to connect to other elements in system 400. In some embodiments of the disclosure, P-P interface 417 and P-P interface 422 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used. [00137] In some embodiments, chipset 420 can be configured to communicate with processor 410, the processor N 405, display device 440, and other devices 472, 476, 474, 460, 462, 464, 466, 477, etc. Chipset 420 may also be coupled to the wireless antenna 478 to communicate with any device configured to transmit and/or receive wireless signals.
[00138] Chipset 420 connects to display device 440 via interface 426. Display 440 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 410 and chipset 420 are integrated into a single SOC. In addition, chipset 420 connects to bus 450 and/or bus 455 that interconnect various elements 474, 460, 462, 464, and 466. Bus 450 and bus 455 may be interconnected via a bus bridge 472. In one embodiment, chipset 420 couples with a non-volatile memory 460, a mass storage device(s) 462, a keyboard/mouse 464, and a network interface 466 via interface 424 and/or 404, smart TV 476, consumer electronics 477, etc.
[00139] In one embodiment, mass storage device(s) 462 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 466 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a Universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
[00140] While the modules shown in FIG. 4 are depicted as separate blocks within the system 400, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 416 is depicted as a separate block within processor 410, cache memory 416 or selected elements thereof can be incorporated into processor core 412.
[00141] It is noted that the system 400 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-4), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.
[00142] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).
[00143] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.
[00144] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.
[00145] Example 1 is a transistor device, comprising: a substrate; a channel disposed on the substrate; a first oxygen exchange layer disposed on the channel; a second oxygen exchange layer disposed on the channel in a spaced relationship with the first oxygen exchange layer; a source disposed on the first oxygen exchange layer; a drain disposed on the second oxygen exchange layer; a gate disposed on the channel between the source and the drain. In example 2, the device of example 1 can optionally include the channel comprising an amorphous oxide semiconductor. In example 3, the device of any one of examples 1-2 can optionally include the channel comprising at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide. In example 4, the device of any one of examples 1-3 can optionally include the substrate comprising silicon, germanium, or a III-V semiconductor. In example 5, the device of any one of examples 1- 4 can optionally include the oxygen exchange layer comprising a reactive metal. In example 6, the device of any one of examples 1-5 can optionally include the reactive metal comprising aluminum, hafnium, or titanium. In example 7, the device of any one of examples 1-6 can optionally include the source comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel. In example 8, the device of any one of examples 1-7 can optionally include the drain comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel. In example 9, the device of any one of examples 1-8 can optionally include one or more spacers disposed on the channel between the gate and one of the drain or the source. In example 10, the device of any one of examples 1-9 can optionally include the oxygen exchange layer having a thickness of about 1 nanometer to about 10 nanometers. In example 11, the device of any one of examples 1-10 can optionally include the channel having a thickness of about 5 nanometers to about 30 nanometers.
[00146] Example 12 is a method for fabricating a device, the method comprising: providing a substrate; depositing a channel on the substrate; depositing a first oxygen exchange layer on the channel; depositing a second oxygen exchange layer on the channel in a spaced relationship with the first oxygen exchange layer; depositing a source on the first oxygen exchange layer; depositing a drain on the second oxygen exchange layer; depositing a gate on the channel between the source and the drain. In example 13, the method of example 12 can optionally include annealing at least one of the first oxygen exchange layer or the second oxygen exchange layer. In example 14, the method of any one of examples 12-13 can optionally include the annealing of the first oxygen exchange layer or the second oxygen exchange layer performed at about 200 degrees centigrade to about 400 degrees centigrade. In example 15, the method of any one of examples 12-14 can optionally include the annealing of the first oxygen exchange layer or the second oxygen exchange layer performed for a duration of about 15 minutes. In example 16, the method of any one of examples 12-15 can optionally include the depositing at least one of the channel, the first oxygen exchange layer , the second oxygen exchange layer , the source, the drain, or the gate performed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In example 17, the method of any one of examples 12-16 can optionally include depositing the channel comprising depositing an amorphous oxide semiconductor. In example 18, the method of any one of examples 12-17 can optionally include depositing the channel comprising depositing at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide. In example 19, the method of any one of examples 12-18 can optionally include depositing the substrate comprising depositing at least one of silicon, germanium, or a III-V semiconductor. In example 20, the method of any one of examples 12-19 can optionally include depositing the oxygen exchange layer comprising depositing a reactive metal. In example 21, the method of any one of examples 12-20 can optionally include depositing the reactive metal comprising depositing at least one of aluminum, hafnium, or titanium. In example 22, the method of any one of examples 12-21 can optionally include depositing the drain comprising depositing at least one of a metal, the metal including tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel. In example 23, the method of any one of examples 12-22 can optionally include depositing one or more spacers disposed on the channel between the gate and one of the drain or the source. In example 24, the method of any one of examples 12-23 can optionally include depositing the oxygen exchange layer comprising depositing the oxygen exchange layer having a thickness of about 1 nanometer to aboutlO nanometers. In example 25, the method of any one of examples 12-24 can optionally include depositing the channel comprising depositing the channel having a thickness of about 5 nanometers to about 30 nanometers.
[00147] Example 26 is a system comprising: a device, the device comprising: a substrate; a channel disposed on the substrate; a first oxygen exchange layer disposed on the channel; a second oxygen exchange layer disposed on the channel in a spaced relationship with the first oxygen exchange layer; a source disposed on the first oxygen exchange layer; a drain disposed on the second oxygen exchange layer; a gate disposed on the channel between the source and the drain. In example 27, the system of example 26 can optionally include the channel comprising an amorphous oxide semiconductor. In example 28, the system of any one of examples 26 or 27 can optionally include the channel comprising at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide. In example 29, the system of any one of examples 26-28 can optionally include the substrate comprising silicon, germanium, or a III-V semiconductor. In example 30, the system of any one of examples 26-29 can optionally include the oxygen exchange layer comprising a reactive metal. In example 31, the system of any one of examples 26-30 can optionally include the reactive metal comprising aluminum, hafnium, or titanium. In example 32, the system of any one of examples 26-31 can optionally include the source comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel. In example 33, the system of any one of examples 26-32 can optionally include the drain comprising a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel. In example 34, the system of any one of examples 26-33 can optionally include one or more spacers disposed on the channel between the gate and one of the drain or the source. In example 35, the system of any one of examples 26-34 can optionally include the oxygen exchange layer having a thickness of about 1 nanometer to about 10 nanometers. In example 36, the system of any one of examples 26-35 can optionally include the channel having a thickness of about 5 nanometers to about 30 nanometers. [00148] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. [00149] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.
[00150] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non- limiting sense.
[00151] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the disclosure is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

CLAIMS The claims are as follow:
1. A transistor device, comprising:
a substrate;
a channel on the substrate;
a first oxygen exchange layer on the channel;
a second oxygen exchange layer on the channel in a spaced relationship with the first oxygen exchange layer;
a source on the first oxygen exchange layer;
a drain on the second oxygen exchange layer;
a first depletion layer in the channel proximate the first oxygen exchange layer; a second depletion layer in the channel proximate the second oxygen exchange layer; and
a gate on the channel between the source and the drain.
2. The device of claim 1, wherein the channel comprises an amorphous oxide semiconductor.
3. The device of claim 1, wherein the channel comprises at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide.
4. The device of claim 1, wherein the substrate comprises silicon, germanium, or a III-V semiconductor.
5. The device of claim 1, wherein the first oxygen exchange layer comprises a reactive metal.
6. The device of claim 5, wherein the reactive metal comprises aluminum, hafnium, or titanium.
7. The device of claim 1, wherein the source comprises a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
8. The device of claim 1, wherein the drain comprises a metal, the metal including at least one of tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
9. The device of claim 1, further comprising one or more spacers on the channel between the gate and at least one of the drain or the source.
10. The device of claim 1, wherein the oxygen exchange layer has a thickness of about 1 nanometer to about 10 nanometers.
11. The device of claim 1, wherein the channel has a thickness of about 5 nanometers to about 30 nanometers.
12. A method for fabricating a device, the method comprising:
providing a substrate;
depositing a channel on the substrate;
depositing a first oxygen exchange layer on the channel;
depositing a second oxygen exchange layer on the channel in a spaced relationship with the first oxygen exchange layer;
depositing a source on the first oxygen exchange layer;
depositing a drain on the second oxygen exchange layer;
depositing a gate on the channel between the source and the drain.
13. The method of claim 12, further comprising annealing the first oxygen exchange layer and the second oxygen exchange layer to form a first depletion layer associated with the source and a second depletion layer associated with the drain.
14. The method of claim 13, wherein the annealing of the first oxygen exchange layer or the second oxygen exchange layer is performed at about 200 degrees centigrade to about 400 degrees centigrade.
15. The method of claim 13, wherein the annealing of the first oxygen exchange layer or the second oxygen exchange layer is performed for a duration of about 15 minutes.
16. The method of claim 12, wherein the depositing of at least one of the channel, the first oxygen exchange layer , the second oxygen exchange layer , the source, the drain, or the gate comprises depositing using physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
17. The method of claim 12, wherein depositing the channel comprises depositing an amorphous oxide semiconductor.
18. The method of claim 12, wherein depositing the channel comprises depositing at least one of zinc oxide, indium gallium zinc oxide, indium tin oxide, or antimony oxide.
19. The method of claim 12, wherein depositing the substrate comprises depositing at least one of silicon, germanium, or a III-V semiconductor.
20. The method of claim 12, wherein depositing the oxygen exchange layer comprises depositing a reactive metal.
21. The method of claim 20, wherein depositing the reactive metal comprises depositing at least one of aluminum, hafnium, or titanium.
22. The method of claim 12, wherein depositing the drain comprises depositing at least one of a metal, the metal including tungsten, titanium nitride, aluminum, titanium, tantalum nitride, cobalt, or nickel.
23. The method of claim 12, further comprising depositing one or more spacers on the channel between the gate and one of the drain or the source.
24. The method of claim 12, wherein depositing the oxygen exchange layer comprises depositing the oxygen exchange layer having a thickness of about 1 nanometer to aboutl O nanometers.
25. The method of claim 12, wherein depositing the channel comprises depositing the channel having a thickness of about 5 nanometers to about 30 nanometers.
PCT/US2017/025537 2017-03-31 2017-03-31 Transistors with oxygen exchange layers in the source and drain WO2018182726A1 (en)

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