WO2019005086A1

WO2019005086A1 - Suppression of current leakage in p-type finfet devices

Info

Publication number: WO2019005086A1
Application number: PCT/US2017/040155
Authority: WO
Inventors: Luis Felipe GILES; Philipp Riess; Uwe Hodel; Wolfgang Molzer; Peter Baumgartner
Original assignee: Intel IP Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

Disclosed herein are semiconductor layers with modified doping profiles for forming P-type (PMOS) FinFET structures, and related methods and devices. One exemplary semiconductor layer with a modified doping profile includes a plurality of regions with different dopant concentrations, the plurality of regions including an N-well region, a P-well region, a low-doped buffer region, and a connection region. The low-doped buffer region separates the P-well region and the N-well region and has P-type dopants with a dopant concentration less than that of any regions within the P-well region. The connection region also has P-type dopants but in concentration higher than that of the low-doped buffer region. The connection region is provided over the low-doped buffer region, between the P-type region and the N-well region, connecting the P-well region and the N-well region. Providing the low-doped buffer region together with the connection region may significantly reduce leakage current in PMOS FinFETs.

Description

SUPPRESSION OF CURRENT LEAKAGE IN P-TYPE FINFET DEVICES

Technical Field

[0001] This disclosure relates generally to the field of semiconductor devices, and more specifically, to suppression of current leakage in P-type FinFETs.

Background

[0002] Metal-oxide-semlconductor (MOS) transistors can be N-type or P-type. In a P-type MOS (P OS) transistor, a body region is made of an IM-type semiconductor material (i.e. a semiconductor material where electrons are the majority carriers and holes are the minority carriers), while source and drain regions are made of P-type semiconductor materials {i.e. semiconductor materials where holes afe the majority carriers and electrons are the minority carriers).

[0003] MOS transistors can have planar or non-planar architecture. Recently, MOS field-effect transistors (MOSFETs) with non-planar architecture have been extensively explored as alternatives to transistors with planar architecture. FinFET is an example of such a non-planar transistor, where a fin, formed of one or more semiconductor materials, extends away from a base. A portion of a fin that is closest to the base is enclosed by a transistor dielectric material. Such a dielectric material, typically an oxide, is commonly referred to as a "shallow trench isolation" (STI), and the portion of the fin enclosed by the STI is referred to as a "sub-fin portion" or simply a "sub-fin." A gate stack that includes at least a layer of a gate electrode metal and a layer of a gate dielectric is provided over the top and sides of the remaining upper portion of the fin (i.e. the portion above and not enclosed by the STI), thus wrapping around the upper portion of the fin and forming a three-sided gate of a FinFET. The portion of the fin wrapped around by the gate stack is commonly referred to as an "active region," "channel portion," or as an "active fin." FinFETs are sometimes referred to as "tri- gate transistors," where the name "tri-gate" originates from the fact that, in some implementations, such transistors may form conducting channels on three "sides" of the fin. However, in other implementations, FinFETs may be dual-gate. FinFETs potentially improve performance relative to planar transistors such as e.g. single-gate transistors.

[0004] The performance of a transistor may depend on a number of factors. One factor is how a transistor of a given type and architecture behaves in terms of current leakage. Reducing current leakage improves transistor performance. While various mechanisms addressing current leakage exist for transistors having planar architecture, a straight-forward translation of such mechanisms to FinFETs is not always possible, in particular for high-voltage/high-frequency transistors used e.g. in power management integrated circuits (PMIC) and radio frequency integrated circuits ( FIC).

Therefore, improvements with respect to suppression of current leakage in FinFETs, in particular in P-type FinFETs able to provide higher voltage capability, would be desirable. Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIGS. 1A and IB are different cross-sectional views of an exemplary conventional FinFET transistor.

[0007] FIGS. 2A and 2B are different cross-sectional views of an exemplary conventional extended drain (ED) MOS transistor (EDMOS) implemented as a FinFET.

[0008] FIGS. 3A-3C are different cross-sectional views of an example FinFET implementing ED concept with a modified doping profile, in accordance with a first embodiment of the present disclosure.

[0009] FIGS. 4A-4C are different cross-sectional views of an example FinFET implementing ED concept with a modified doping profile, in accordance with a second embodiment of the present disclosure.

[0010] FIG. 5 is a flow diagram of an example method of manufacturing a FinFET implementing ED concept with a modified doping profile, in accordance with various embodiments of the present disclosure.

[0011] FIGS. 6A and 6B are top views of a wafer and dies that include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein.

[0012] FIG. 7 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein.

[0013] FIG. 8 is a cross-sectional side view of an IC device assembly that may include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein.

[0014] FIG. 9 is a block diagram of an example computing device that may include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein.

Detailed Description

[0015] Disclosed herein are semiconductor layers with modified doping profiles for forming P-type FinFETs implementing an extended drain (ED) concept (i.e. a transistor architecture where a highly doped (HD) drain region of a transistor is not adjacent to the gate of the transistor but instead is embedded inside a lateral extended drain region which has a moderate doping concentration), and related methods and devices. One exemplary semiconductor layer with a modified doping profile includes a plurality of regions with different dopant concentrations, the plurality of regions including an N-well region comprising an N-type region (i.e. a region of one or more semiconductor materials doped with N-type dopants), a P-well region comprising one or more P-type regions (i.e. regions of one or more semiconductor materials doped with P-type dopants), a low-doped buffer region between (i.e. separating) the P-well region and the N-well region, the low-doped buffer region having P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and a connection region provided over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region. The connection region connects the P-well region and the N-well region, i.e. one end of the connection region is in contact with a portion of the P-well region and another end of the connection region is in contact with a portion of the N-well region. In the ON state, the connection region connects the MOSFET channel with the extended drain region.

[0016] As described in greater detail below, providing the low-doped buffer region which has a low dopant concentration and, therefore, has low conductivity for the charge carriers of the current in the ON and OFF states of a PMOS transistor (e.g. a P-type FinFET), together with a higher-doped P- type semiconductor of the connection region (i.e. a region which is conductive for the charge carriers of the current in the ON and OFF states of a PMOS transistor), substantially reduces cross- leakage current (i.e. current coming from the sub-fin towards the fin region) and substantially reduces the ON-resistance (i.e. the resistance between the drain and source terminals when the MOSFET is in the ON state) of a PMOS transistor. As a result, a transistor can be more robust against trap-induced drain leakage and the overall leakage current may be significantly reduced (e.g.

reduced by several orders of magnitude).

[0017] FinFETs implementing ED concept with modified doping profiles as described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0018] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well known features are omitted or simplified in order not to obscure the illustrative implementations.

[0019] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown, by way of illustration, embodiments that may be practiced. The accompanying drawings are not necessarily drawn to scale. For example, to clarify various layers, structures, and regions, the thickness of some layers may be enlarged. Furthermore, while drawings illustrating various structures/assemblies of exemplary devices may be drawn with precise right angles and straight lines, real world process limitations may prevent implementations of devices exactly as shown. Therefore, it is understood that such drawings revised to reflect example real world process limitations, in that the features may not have precise right angles and straight lines, are within the scope of the present disclosure. Drawings revised in this manner may be more representative of real world structure/assemblies as may be seen on images using various characterization tools, such as e.g. scanning electron microscopy (SEM) or transmission electron microscopy (TEM). In addition, the various structures/assemblies of the present drawings may further include possible processing defects, such as e.g. the rounding of corners, the drooping of the layers/lines, unintentional gaps and/or discontinuities, unintentionally uneven surfaces and volumes, etc., although these possible processing defects may not be specifically shown in the drawings. It is to be understood that other embodiments may be utilized and structural or logical changes to the drawings and descriptions may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0020] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. [0021] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0022] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Furthermore, stating in the present disclosure that any part (e.g. a layer, film, area, or plate) is in any way positioned on or over (e.g. positioned on/over, provided on/over, located on/over, disposed on/over, formed on/over, etc.) another part means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located

therebetween. On the other hand, stating that any part is in contact with another part means that there is no intermediate part between the two parts.

[0023] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0024] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. In some examples, as used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. In another example, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. [0025] Specific to the embodiments of the present disclosure, the term "HD drain region" refers to a portion of the P-well of a P-type transistor (i.e. a region of a P-type semiconductor material) having a dopant concentration that is higher than that between that portion (i.e. the HD drain region) and the source region. As used herein, a region of one or more P-type semiconductor materials (i.e. one or more extrinsic semiconductor materials created by doping an intrinsic semiconductor material with donor impurities such as e.g. boron or indium if the intrinsic semiconductor material is silicon) may simply be referred to as a "P-type semiconductor" even though it may include more than one P- type semiconductors, and may omit the word "region." Similarly, as used herein, a region of one or more N-type semiconductor materials (i.e. one or more extrinsic semiconductor materials created by doping an intrinsic semiconductor material with acceptor impurities such as e.g. phosphorus or arsenic if the intrinsic semiconductor material is silicon) may also omit the word "region," and may simply be referred to as an "N-type semiconductor" even though it may include more than one N- type semiconductors. The terms "N-well region" and "P-well region" of a transistor may also omit the word "region" and be simply referred to as "N-well" and "P-well." As is well known, the terms "N-well" and "P-well" refer to regions which are created by either deposition or dopant implantation of, respectively, N-type and P-type dopants in a highly crystalline layer provided over, or being in the uppermost part of a substrate (e.g. the highly crystalline layer 240/340 described herein) for the purpose of providing a P-N junction under or aligned with an edge of a gate stack in order to enable transistor operation.

[0026] For purposes of illustrating FinFETs implementing ED concept with modified doping profiles as proposed herein, it is important to understand the phenomena that may come into play in a typical FinFET. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0027] As described above, FinFETs refer to transistors having a non-planar architecture where a fin, formed of one or more semiconductor materials, extends away from a base. An example of a FinFET is shown in FIGs. 1A and IB, illustrating two different cross-sectional views of an exemplary conventional FinFET 100.

[0028] FIG. 1A illustrates a side view of the FinFET 100, with a cross-section taken along the length of the fin, while FIG. IB illustrates a front view of the FinFET 100 with a cross-section taken across the gate of the FinFET - i.e. FIG. IB illustrates a cross-sectional view with a cross-section taken along a plane AA shown in FIG. 1A, while FIG. 1A illustrates a cross-sectional view with a cross-section taken along a plane BB shown in FIG. IB (if the length of the fin is in the direction of a y-axis of a conventional x-y-z coordinate system, then FIG. 1A is a cross-sectional view with a cross-section taken along a z-y plane, while FIG. IB is a cross-sectional view with a cross-section taken along a z-x plane).

[0029] As shown in FIGS. 1A and IB, the FinFET 100 typically includes a substrate 102 over which a highly crystalline (e.g. epitaxially grown) semiconductor layer (i.e. a layer of one or more

semiconductor materials) 104 is provided. The semiconductor layer 104 is commonly referred as a "channel material" or simply a "channel" because, during operation, a channel of a transistor is formed in a portion of this layer. In a FinFET, a portion of the channel material 104 is formed as a fin 120 extending away from the substrate (the fin 120 is not specifically shown in FIG. 1A because FIG. 1 illustrates a cross-sectional view with a cross-section taken along the length of the fin 120, but can be better seen in FIG. IB). A gate stack 122 including a gate electrode material 106 and a gate dielectric 108, typically a high-k dielectric material, wraps around the upper portion of the fin 120, as can be seen in FIG. IB, with the active region of the channel material 104 (i.e. the region where the transistor channel is formed during operation) corresponding to the portion of the fin 120 wrapped by the gate stack. In particular, as shown in FIG. IB, the high-k dielectric 108 may wrap around the upper portion of the fin 120 and the gate electrode material 106 may wrap around the high-k dielectric 108. As also shown in FIG. IB, sides of the lower portion of the fin 120, i.e. a portion that is closest to the substrate 102, are enclosed by an STI 112. As previously described herein, a portion of a fin, e.g. the fin 120, that is enclosed by an STI is typically referred to as a "sub-fin" while a portion of a fin over which a gate stack wraps around is typically referred to as an "active fin" or a "channel portion." In general, a gate stack includes a stack of one or more gate electrode metals and a stack of one or more gate dielectrics and is provided over the top and sides of the upper portion of the fin (i.e. the portion above the STI), thus wrapping around the upper portion of the fin and forming e.g. a three-sided gate of a tri-gate transistor.

[0030] FIG. 1A further illustrates source and drain electrodes 124 and 126 formed of one or more electrically conductive materials 110, electrically connected to, respectively, a source region 134 and an HD drain region 136. As is known in the art, source/drain (S/D) regions of a transistor (also sometimes interchangeably referred to as "diffusion regions") are regions of doped semiconductors, e.g. regions of doped channel material, so as to supply charge carriers for the transistor channel. Often, the S/D regions are highly doped, e.g. with dopant concentrations of at least above 1-10²¹ dopants per cubic centimeter (cm ³), in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations in some implementations. Regardless of the exact doping levels, the S/D regions 134 and 136 are the regions having dopant concentration higher than in other regions, e.g. in between the source region 134 and the drain region 136, and, therefore, are referred to as HD S/D regions. Reference numeral 128 shown in FIG. 1A illustrates a channel region of the FinFET 100.

[0031] As also described above, performance of a transistor depends on current leakage. For example, Gate Induced Drain Leakage (GIDL) causes an early junction breakdown (also known as the "Zener's breakdown"), severely degrading transistor performance. This problem is particularly prominent for otherwise promising high-voltage MOSFETs.

[0032] Band-to-band tunneling is the most widely acknowledged mechanism responsible for GIDL. GIDL occurs predominantly in the region where the HD drain region is adjacent to or overlaps the gate (i.e. is adjacent to or overlaps the channel material under the gate stack) where the gate work function and high drain doping concentration enhance the electric field, triggering the band-to-band tunneling of carriers. Therefore, a conventional FinFET device such as the one shown in FIGS. 1A and IB, with its HD drain region being adjacent to the gate stack, is not the first choice to build a high- voltage device. Instead, the most used approach conventionally used to improve on GIDL is a so- called extended drain (ED) MOS (EDMOS), an example of which is illustrated in FIGS. 2A-2B.

[0033] FIG. 2A is a cross-sectional side view of an EDMOS FinFET transistor 200, similar to the view of FIG. 1A, where the same reference numerals as those shown in FIGS. 1A-1B illustrate the same or analogous elements, description of which is not, therefore, repeated in detail. As the acronym implies, the EDMOS concept requires an extended drain field region with the HD drain region 136 being physically separated from the gate stack 122, e.g. by a dummy drain electrode 226 and a dummy gate electrode 222, as shown in FIG. 2A.

[0034] FIG. 2A further illustrates that a semiconductor layer 204, which is a layer similar to the semiconductor/channel layer 104, typically includes a plurality of regions of varying dopant concentrations.

[0035] As shown in FIG. 2A, the lowest portion of the semiconductor layer 204 is typically a P-type semiconductor layer 240 that serves as a basis for later forming the body region of a transistor. Such a layer is typically provided to serve as a highly crystalline layer, e.g. epitaxially grown, that is a foundation for building a transistor. The P-type layer 240 is referred to in the following as "low- doped" because the dopant concentration of the semiconductor layer 204 is the lowest in the layer 240, out of all of the regions present within the semiconductor layer 204.

[0036] As also shown in FIG. 2A, the HD source region 134 and the HD drain region 136 as described above, except that now the HD drain region 136 is now laterally removed from the gate stack 122, are in the upper portions of the semiconductor layer 204 (i.e. in the portions closest to the surface of the semiconductor layer 204). In addition, FIG. 2A further illustrates that the upper portions of the semiconductor layer 204 further include, in a PMOS transistor, an N-well region 244 and a P-well region 246, each of which is a region of a moderate dopant concentration (i.e. lower than that of the HD S/D regions 134/136 but higher than that of the low-doped layer 240). The P-well region 246 is a region of moderate P-type doping concentration extending from the HD drain region 136 towards, but not reaching, the source region 134. Instead, the P-well region 246 comes into contact with the N-well region 244 extending from the HD source region 134, the N-well region 244 being a region of moderate N-type doping concentration. Namely, the P-well region 246 extends, from the edge of the gate stack 122 closest to the HD drain region 136, towards the source region 134, under the gate stack 122, by a length shown in FIG. 2A as a length "CD2." In this manner, contrary to a conventional MOSFET as e.g. shown in FIGS. 1A-1B, the gate stack 122 is provided over a P-N junction formed where the N-type semiconductor of the N-well 244 interfaces the P-type semiconductor of the P- well 246, which reduces the electric field near the gate edge directly impacting band-to-band tunneling and, therefore, reducing GIDL. A dimension shown in FIG. 2A as "CD1" then refers to the actual channel length, i.e. a distance between the source region 134 and the P-well 246, while a dimension shown in FIG. 2A as "CD3" refers to the distance by which the HD drain region 136 is laterally/horizontally shifted away from the edge of the gate stack 122 that is closest to the HD drain region. Thus, the gate length L_g, also indicated in FIG. 2A, is equal to the sum of CD1 and CD2. In such an EDMOS design, CD1 may be equal to CD2 and equal to e.g. 100 nm, while CD3 is typically between about 500 and 1000 nm (one to two poly pitches).

[0037] In various embodiments, the bottoms of the N-well 244 and the P-well 246 do not have to be aligned as shown in FIG. 2A. Each of the HD source region 134, the HD drain region 135, the N- well region 244, the P-well region 246, and the low-doped semiconductor layer 240 is a region of highly crystalline semiconductor material (e.g. epitaxially grown), with the methods for providing such regions/layers being known in the art. In general, such regions are either provided by dopant implantation of dopants of appropriate type and concentration into the highly crystalline low-doped layer 240 (i.e. these regions are built within, or out of, the low-doped layer 240 provided over the substrate 102), or by removing portions of the highly crystalline low-doped layer 240 (e.g. by etching) and depositing highly crystalline doped semiconductors with dopants of appropriate type and concentration into the openings formed by the removal.

[0038] FIG. 2B is a cross-sectional side view of the EDMOS FinFET transistor 200, similar to the view of FIG. 2A, showing a front view of the FinFET 200 with a cross-section taken along a plane AA shown in FIG. 2A (i.e. across the fin 120). On the other hand, FIG. 2A illustrates a cross-sectional view with a cross-section taken along a plane BB shown in FIG. 2B. Similar to FIGS. 1A-1B, if the length of the fin is in the direction of a y-axis of a conventional x-y-z coordinate system, then FIG. 2A is a cross- sectional view with a cross-section taken along a z-y plane, while FIG. 2B is a cross-sectional view with a cross-section taken along a z-x plane.

[0039] Because the HD drain region 136 of the EDMOS FinFET transistor 200 is shifted away from the gate stack 122, GIDL is reduced. However, while such EDMOS approach may be an improvement over a conventional FinFET that does not implement the ED concept, because the conventional EDMOS was not specifically designed for FinFET technology, such a straight-forward translation of the ED concept to FinFETs is not necessarily the most optimal. In particular, leakage current is believed to pass through the sub-fin portion of the fin 120 (i.e. the portion of the fin 120 that is surrounded by the STI 112). The interfaces between the sub-fin portion of the fin 120 and the STI 112 (shown with two thick black vertical lines in the view of FIG. 2B) are often of bad quality in that they contain a lot of traps (i.e. sites where charge carriers may be trapped) or even extended defects such as e.g. threading dislocations or stacking faults which are crystallographic defects generated by self-interstitial agglomeration. The bad quality of these interfaces may increase trap-induced leakage, which may heavily increase drain leakage. One way to reduce this trap-induced leakage may be to improve the interface quality of the sub-fin/STI (e.g. Si/Si oxide) interfaces. However, this may prove cumbersome due to the different thermal anneal steps typically required in order to improve such interface quality and also due to the possibility that traps may still be present at different locations along the STI/sub-fin interfaces even after the interface healing process.

Embodiments of the present disclosure aim to provide an improvement to FinFETs implementing the ED concept, in particular P-type FinFETs, by implementing a semiconductor/channel layer similar to the semiconductor layer 204 but with additional, carefully selected doped regions which, together, make a FinFET more robust against trap-induced drain leakage by re-directing drain leakage current into the active fin region. In other words, embodiments of the present disclosure do not necessarily get rid of the drain leakage current altogether, but, instead, re-direct that current into the high- quality active fin, thereby reducing/suppressing leakage current compared to implementations as shown in FIGS. 2A-2B.

[0040] Two sets of figures, FIGS. 3A-3C and FIGS. 4A-4C illustrate different embodiments of how semiconductor layers similar to the semiconductor layer 204, but now with different modified doping profiles, may be implemented within a P-type FinFET 300 - these semiconductor layers indicated in the two sets of figures as different versions of a semiconductor layer 304. What both of the embodiments have in common is the presence of a low-doped buffer region 348 separating a P- well region 346 and an N-well region 344, and the presence of a connection region 350, provided over the low-doped buffer region 348, connecting the P-well region 346 and the N-well region 344. [0041] FIGS. 3A-3C are different cross-sectional views of an example FinFET 300 implementing ED concept with a semiconductor layer 304 having a modified doping profile in accordance with a first embodiment of the present disclosure. FIG. 3A illustrates a side view, i.e. a cross-section taken along the length of the fin, similar to that shown in FIG. 1A and FIG. 2A, while each of FIGS. 3B and 3C illustrates a front view of the FinFET 300 with a cross-section taken across different front views of the FinFET 300. In particular, FIG. 3B illustrates a cross-sectional view with a cross-section taken along a plane A1A1 shown in FIG. 3A, while FIG. 3A illustrates a cross-sectional view with a cross- section taken along a plane BB shown in FIG. 3B. Similarly, FIG. 3C illustrates a cross-sectional view with a cross-section taken along a plane A2A2 shown in FIG. 3A, while FIG. 3A illustrates a cross- sectional view with a cross-section taken along a plane CC shown in FIG. 3C. If the length of a fin 320 shown in FIGS. 3A-3C is in the direction of a y-axis of a conventional x-y-z coordinate system, then FIG. 3A is a cross-sectional view with a cross-section taken along a z-y plane, while each of FIGS. 3B and 3C is a cross-sectional view with a cross-section taken along different z-x planes.

[0042] Similar to the FinFETs 100 or 200, the FinFET 300 includes a substrate 302 over which a semiconductor layer 304 is provided.

[0043] The substrate 302 may be any structure on which one or FinFETs implementing ED concept with modified doping profiles as described herein can be disposed. In some embodiments, the substrate 302 may include a semiconductor, such as silicon. In some embodiments, the substrate 302 may include an insulating layer, e.g. an Inter Layer Dielectric (ILD) material such as an oxide isolation layer, e.g. to electrically isolate the semiconductor material of the substrate 302 from e.g. the S/D regions and the semiconductor layer 304, and thereby mitigate the likelihood that a conductive pathway will form between the HD source region 334 and the HD drain region 336 through the substrate 302. Examples of ILDs that may be included in/on a substrate 302 in some embodiments may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. Any suitable ones of the embodiments of the substrate 302 described with reference to FIG. 3 may be used for the substrate of others of the FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein.

[0044] The semiconductor layer 304 may be a highly crystalline (e.g. epitaxially grown)

semiconductor layer (i.e. a layer of one or more semiconductor materials) composed of

semiconductor material systems suitable for implementing a P-type FinFET, some of which material systems are N-type semiconductors and some of which are P-type semiconductors, as described below.

[0045] As shown in FIGS. 3A-3C, at least a portion of the semiconductor layer 304 is formed as a fin 320 extending away from the substrate (two different views of the FinFET 300 with the fin 320 in a cross-section across the fin are shown in FIGS. 3B and 3C). Similar to the FinFET 200, the upper portion of the fin 320 is wrapped by a gate stack 322 including a gate electrode material 306 and a gate dielectric 308, with the active fin portion of the semiconductor layer 304 corresponding to the portion of the fin wrapped by the gate stack. In particular, the gate dielectric 308 may wrap around the upper portion of the fin 320 and the gate electrode material 306 may wrap around the gate dielectric 308.

[0046] Although the fin 320 illustrated in FIGS. 3A-3C is shown as having a rectangular cross-section, the fin 320 may instead have a cross-section that is rounded or sloped at the "top" of the fin 320, and the gate stack 322 may conform to this rounded or sloped fin 320. In use, the FinFET 300 may form conducting channels on three "sides" of the fin 320 wrapped around by the gate stack 322, potentially improving performance relative to single-gate transistors (which may form conducting channels on one "side" of a channel material or substrate) and double-gate transistors (which may form conducting channels on two "sides" of a channel material or substrate).

[0047] Since the FinFET 300 is a P-type metal-oxide-semiconductor (PMOS) FinFET, the gate electrode material 306 may include at least one P-type work function metal, such as, but not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). In some embodiments, the gate electrode material 306 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 306 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in FIGS. 3A-3C.

[0048] In some embodiments, the gate dielectric 308 may be a high-k dielectric (i.e. a dielectric material that has a higher dielectric constant (k) than silicon dioxide) including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 308 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0049] In some embodiments, an annealing process may be carried out on the gate dielectric 308 during manufacture of the transistor 300 to improve the quality of the gate dielectric 308. The gate dielectric 308 may have a thickness, a dimension measured in the direction of the z-axis shown in FIGS. 3A-3C, that may, in some embodiments, be between about 0.4 nanometers and 5 nanometers, including all values and ranges therein (e.g., between about 0.5 and 3 nanometers, or between 1 and 2 nanometers).

[0050] In some embodiments, the gate stack 322 of the gate dielectric material 308 and the gate electrode material 306 may be surrounded by a gate spacer, not shown in FIG. 3, configured to provide separation between the gates of different transistors. Such a gate spacer is typically made of a low-k dielectric material (i.e. a dielectric material that has a lower dielectric constant (k) than silicon dioxide). Examples of low-k materials that may be used in such a dielectric spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g. polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as e.g.

hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used in a dielectric spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.

[0051] Similar to the FinFET 100 and FinFET 200, the lower portion of the fin 320 of the FinFET 300, i.e. the sub-fin of the fin 320, is surrounded by a dielectric material, shown in the views of FIGS. 3B and 3C as STI 312. The dielectric material of the STI layer 312 may e.g. include any of the low-k or high-k dielectric materials described herein including but not limited to elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Further examples of dielectric materials that may be used in the STI material 312 may include, but are not limited to silicon nitride, silicon oxide, silicon dioxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0052] FIG. 3A further illustrates source and drain electrodes 324 and 326 formed of one or more electrically conductive materials 310, electrically connected to, respectively, the HD source region 334 and the HD drain region 336. The S/D electrode material 310 may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the S/D electrode material 310 may include one or more metals or metal alloys, with metals such as e.g. ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, the S/D electrode material 310 may include one or more electrically conductive alloys, oxides, carbides, or nitrides of one or more metals. In various embodiments, the S/D conductive material 310 could be the same or different materials for the source electrode 324 and the drain electrode 326, and could be the same or different materials as the gate electrode material 306. In various embodiments, the S/D electrode material 310 may have a thickness between about 5 and 500 nm, including all values and ranges therein, e.g. between 5 and 100 nm.

[0053] Turning now to the various regions included in the semiconductor layer 304, similar to the semiconductor layer 204 of the FinFET 200, the semiconductor layer 304 includes a low-doped layer 340, similar to the low-doped layer 240, described above. Thus, the low-doped layer 340 is a P-type semiconductor layer that serves as a basis for the body region of the NMOS FinFET 300, referred to as "low-doped" because the dopant concentration of the semiconductor layer 304 is the lowest in the layer 340, out of all of the regions present within the semiconductor layer 304.

[0054] Further, also similar to the FinFET 200, the semiconductor layer 304 of the FinFET 300 includes an HD source region 334 and an HD drain region 336 on either side of the gate stack 322, the HD S/D regions 334 and 336 provided within the fin 320 and having the highest dopant concentrations of all of the regions present within the semiconductor layer 304 (both with P-type dopants, since the FinFET 300 is a PMOS transistor). Similar to the FinFET 200, while the source region 334 may be provided adjacent to the gate stack 322 (or could be overlapping with the gate stack, i.e. a portion of the source region 334 could be below the gate stack 322), the HD drain region 336 is laterally/horizontally shifted away from the gate stack by a distance CD3, as shown in FIG. 3A. In other words, lateral/horizontal shift by the distance CD3 means that the edge of the HD drain region 336 closest to the edge of the gate stack 322 is separated from the gate stack 322 by that distance, as illustrated with showing the distance CD3 in FIG. 3A, or, equally, the distance CD3 represents the distance between the closest two points of the HD drain region and the gate stack (these two points shown in FIG. 3 as a point 360 of the HD drain region 336 and a point 362 of the gate stack 322). The distance CD3 may be of values as described above with reference to the FinFET 200, including all values and ranges therein.

[0055] Also similar to the FinFET 200, the semiconductor layer 304 includes an N-well 344 and a P- well 346, with moderate doping concentrations which are between the low limit of the low-doped layer 340 and the high limit of the HD S/D regions 334 and 336. In contrast to the FinFET 200, the N- well 344 and the P-well 346 of the FinFET 300 do not contact one another. Instead, in the FinFET 300, the low-doped layer 340 extends upwards (in the direction of the z-axis shown in FIGS. 3A-3C), forming a low-doped buffer region 348 separating the N-well 344 and the P-well 346. The low- doped buffer region 340 is made of a semiconductor material having P-type dopants with a dopant concentration less than that of any P-type regions within the P-well 346, thus providing electrical isolation for the charge carriers of the leakage current in the PMOS FinFET 300. Above the low- doped buffer region 348, i.e. in the uppermost layer in a portion of the semiconductor layer 304, is a connection region 350 made of a semiconductor material with P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region 340, thus electrically connecting the N-well 344 and the P-well 346 for the charge carriers of the leakage current in the PMOS FinFET 300. In some embodiments, the dopant concentration of the low-doped buffer region 340 may be about 0.2%-1.0% of the dopant concentration of the connection region 350.

[0056] Providing the low-doped buffer region 348 which has low dopant concentration and, therefore, has relatively low conductivity for the charge carriers of the current in the ON and OFF states of the PMOS FinFET 300, together with a conductive P-type semiconductor of the connection region 350, may ensure that the current path (i.e. area of relatively high conductivity) is restricted to the active fin region. Thus, embodiments of the present disclosure are based on a two-fold idea of 1) increasing doping concentration only in the regions where it is needed to provide conductivity (i.e. adjacent to the channel), and 2) reduce doping concentration in the sub-fin region in order to reduce band-to-band tunneling which ultimately reduces leakage. As a result, the FinFET 300 becomes more robust against trap-induced drain leakage and the leakage current may be significantly reduced (e.g. reduced by several orders of magnitude).

[0057] In some embodiments, the N-well region 344 may connect to the low-doped buffer region 348 and the connection region 350 at a portion of the semiconductor layer under the gate stack at a location other than about the middle of the gate stack 322 as shown in FIG. 3A. In other words, the connection region 350 may extend from the edge of the gate stack 322 closest to the HD drain region 336 (i.e. from the point 360), towards the source region 334, under the gate stack 322, by a length shown in FIG. 3A as a length "CD2," thus forming a P-N junction under the gate stack 322 (i.e. where the N-doped N-well 344 interfaces the P-doped connection layer 350). In such embodiments, a dimension shown in FIG. 3A as "CD1" then refers to the actual channel length, i.e. a distance between the HD source region 334 and the connection layer 350, and, thus, the gate length L_g, indicated in FIG. 3A, is equal to the sum of CD1 and CD2. In some such embodiments, CD1 may be approximately equal to CD2 (i.e. CD1=CD2= L_g /2), as shown in the example of FIG. 3A. However, in other embodiments, CD1 may be smaller than or greater than CD2. Having CD1 smaller than CD2 may result in decreased leakage, while having CD1 greater than CD2 may result in improved performance, e.g. reduced ON-resistance. For example, for a gate length of about 160 nm (i.e. an exemplary high-voltage application), CD1 may be about 40 nm while CD2 may be about 120 nm if low leakage is an important goal, or, if high performance is an important goal, then CD2 may be about 40 nm while CD1 may be about 120 nm. Of course, different division of the gate length into CD1 and CD2 is also possible, for various design requirements, all of which are within the scope of the present disclosure.

[0058] In other embodiments, the N-well region 344 may extend throughout the entire gate length L_g, to the edge of the gate stack 322 indicated by the point 360, thus connecting to the low-doped buffer region 348 and the connection region 350 along the vertical plane aligned with the edge of the gate stack that is closest to the drain (i.e. the edge with the point 360; in other words, CD2 may be equal to zero and L_g =CD1). Such embodiments may result in improved performance, e.g.

reduced ON-resistance.

[0059] In some embodiments, the depths of the P-well 346 and the N-well 344 in the

semiconductor layer 304 may be the same (as was e.g. shown for the FinFET 200). In other embodiments, their depths may be different. For example, as is shown in the example of the FinFET 300, the P-well 346 may extend further away from the upper surface of the semiconductor layer 304, towards the substrate 302, which may be chosen depending upon leakage/performance requirements.

[0060] As described above, each of the P-well 346 and the N-well 344 regions refers to a region having a dopant concentration of, respectively, P-type and N-type dopants, that is lower than the dopant concentration of the HD S/D regions 334 and 336 (both of the latter having P-type dopants since the FinFET 300 is an P-type transistor). For example, each of the P-well 346 and the N-well 344 may have a dopant concentration between about 5-10¹⁶ and 2-10¹⁸ cm ³, while each of the HD drain region 336 and the source region 334 may have a dopant concentration higher than about 2-10¹⁸ cm^" ³, e.g. above 1-10¹⁹ cm^"3, or 1-10²¹ cm^"3. On the other hand, the dopant concentration of the low- doped layer 340 may be about a few percent, e.g. about 1-2%, of that of the P-well 346 and/or the N-well 344.

[0061] In various embodiments, dopant concentrations of the N-well 344 and the P-well 346 may be different from one another (i.e. different in values, since the dopant types of these regions are always different). Similarly, dopant concentrations of the HD S/D regions 334 and 336 may be different from one another (again, different in values, since the dopant types of these regions are always the same for a transistor of a given type, i.e. for a transistor that is either NMOS or PMOS).

[0062] FIG. 3A further illustrates that the semiconductor layer 304 may further include an optional upper P-type region 356, which may be referred to as a "shallow implant" 356.

[0063] For a PMOS FinFET, an optional shallow implant 356 would include P-type dopants, the same as the P-well region 346, and, therefore, may be considered to be a part of the P-well region 346. At least a portion of the shallow implant 356 may be provided between the connection region 350 and the HD drain region 336 (i.e. at least a portion of the shallow implant 356 connects the connection region 350 and the HD drain region 336 of the P-well region 346). In other words, at least a portion of one end of the shallow implant 356 may be in contact with the connection region 350 and another end of the shallow implant 356 may be in contact with the HD drain region 336; thus the connection region 350 is connected to the HD drain region 336 via the shallow implant 356.

Providing the shallow implant 356 with P-type dopants allows to reduce drain resistance, thus advantageously improving transistor performance.

[0064] In various embodiments, a thickness of the shallow implant 356 may be between 5% and 100% of a thickness of the active fin portion fh of the fin. Thus, while FIG. 3A and FIG. 3C illustrate that the bottom of the shallow implant 356 is aligned with the top of the sub-fin portion of the fin (i.e., in such a case, the thickness of the shallow implant 356 is 100% of the thickness of the active fin portion of the fin 320), this is not always the case - e.g. the shallow implant 356 may end without reaching the top of the sub-fin portion of the fin (i.e. be included completely in the active fin portion).

[0065] In various embodiments, a thickness of the connection region 350 may be between 5% and 100% of a thickness of the active fin portion of the fin. In some embodiments, the connection region 350 and the shallow implant region 356 may have about the same thickness. In other embodiments, their thicknesses may be different, e.g. the connection region 350 may have a thickness greater than that of the shallow implant 356 or the shallow implant 356 may have a thickness greater than that of the connection region 350.

[0066] In some embodiments, a dopant concentration of the shallow implant 356 may be higher than a dopant concentration of the connection region 350 (again, both P-type dopants), e.g. the dopant concentration of the connection region 350 may be about 10%- 50% of the dopant concentration of the shallow implant 356. Alternatively or additionally, in some embodiments, a dopant concentration of the shallow implant 356 may be lower than a dopant concentration of the HD drain region 336, e.g. the dopant concentration of the shallow implant 356 may be about 0.2%- 1.0% of the dopant concentration of the HD drain region 336. Thus, the HD drain region 336 is the P- type region with the highest dopant concentration, the shallow implant 356 is the P-type region with the next-highest dopant concentration, followed by the P-type connection region 350, after which comes the rest of the P-well 346, with the low-doped buffer layer 340 having the lowest P-type dopant concentration of all.

[0067] In various embodiments, the length of the connection region 350 (i.e. the dimension measured along the y-axis of the coordinate system shown in FIGS. 3A-3C), and, thus, the width of the low-doped buffer region 348 (also measured along the y-axis) may be between about 25% of Lg (e.g. 40nm) and 75% of Lg (e.g. 120nm), including all values and ranges therein.

[0068] In some of the embodiments where the shallow implant 356 is present, the length of the shallow implant 356 (i.e. the dimension measured along the y-axis of the coordinate system shown in FIGS. 3A-3C) may be equal to the distance between the connection region 350 and the HD drain region 336 (as shown in FIG. 3A), in order to minimize drain resistance. However, in other embodiments, the length of the shallow implant 356 may be less than that distance. Decreasing the length of the shallow implant 356 increases the potential drop near the surface which indirectly decreases the undesirable band-to-band tunneling of carriers at the gate edge.

[0069] In various embodiments, each of the regions of the modified doping profiles of the semiconductor layer 304 described herein, namely the low-doped layer 340, the HD S/D regions 334, 336, the N-well region 344, the P-well region 346, the connection region 350, the low-doped buffer region 348, and the shallow implant 356 may be formed of suitable monocrystalline or highly crystalline semiconductors (e.g. semiconductor material(s) at least 80% of which is in a single crystal/monocrystalline form). Materials in a single crystal form are also referred to as

"monocrystalline solids," i.e. materials in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries. An opposite of a

monocrystalline solid is a fully amorphous material (i.e. no crystallinity at all). In between fully amorphous (no crystallinity) and single crystalline materials (100% single phase single orientation long range order with zero imperfections) there is a wide spectrum of materials with varying level of crystallinity. As used herein, the term "highly crystalline" refers to the materials at least 80% of which is in a single crystal/monocrystalline form but which may also include some defects (e.g. dislocations, grain boundaries, etc.), polycrystals, or other imperfections/issues which make the materials short of being single crystalline. In some embodiments, each of the regions of the semiconductor layer 304 may be a silicon-based semiconductor material or alloy. In some embodiments, each of the regions of the semiconductor layer 304 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., N, P, As, Sb). In some embodiments, each of the regions of the semiconductor layer 304 may be a binary, ternary, or quaternary lll-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth. For exemplary P-type transistor embodiments, each of the regions of the semiconductor layer 304 may advantageously be a lll-V material having a high hole mobility, such as, but not limited to GaN, InGaAs, InGaN, AIGaN, InP, InSb, and InAs. For some such embodiments, the semiconductor layer 304 may be a ternary lll-V alloy, such as InGaAs or GaAsSb. For some ln_xGai-_xAs fin embodiments, indium content in the semiconductor layer 304 may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., lno.7Gao.3As). In some embodiments, each of the regions of the semiconductor layer 304 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the low-doped layer 340 is an intrinsic lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the low- doped layer 340, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the low-doped layer 340 may be relatively low, for example below about 10¹⁵ cm^"3, and advantageously below 10¹³ cm^"3.

[0070] In some embodiments, the semiconductor layer 304 may have a thickness e.g. between about 150 and 1000 nm, including all values and ranges therein, e.g. between about 150 and 600 nm. In some embodiments, the lower and upper bound for the thickness of the semiconductor layer 304 may be expressed in terms of a fin-height (i.e. the height fh of the active fin, i.e. a portion of the fin above the STI), e.g. as 3xfh and 20xfh, respectively, where fh is a fin-height distance used in a particular technology.

[0071] While the embodiments described above are described with reference to various exemplary ranges and/or upper or lower limits for various distances, in general, these distances may be in different ranges depending e.g. on whether a device in which a FinFET such as the FinFET 300 is implemented is intended for high-voltage applications such as e.g. input/output (I/O) devices/drivers or low-voltage applications such as e.g. logic gates. As is known, gate lengths and, correspondingly, poly-pitch distances used in the low-voltage applications are smaller than those used in high-voltage applications. For example, in some embodiments, e.g. those suitable for low-voltage applications, a gate length L_g may be between about 5 and 50 nm, including all values and ranges therein, e.g. between 5 and 20 nm, or between 7 and 10 nm. In other embodiments, e.g. those suitable for low- voltage applications, a gate length L_g may be above 50 nm, e.g. between about 50 and 1000 nm (or even higher), including all values and ranges therein, e.g. between 75 and 200 nm, or between 50 and 100 nm. Thus, in some embodiments, ranges for various distances according to various embodiments of the present disclosure may be expressed in terms of a poly-pitch distance (i.e. a dimension indicative of the distance between the outer edges of two adjacent poly gates) - e.g. the distance CD1 may be between about 1/6 x pp andl/2x pp, including all values and ranges therein, CD2 may be between about l/6x pp and l/2x pp, including all values and ranges therein, CD3 may be between about lx pp and 3x pp, including all values and ranges therein where pp is a poly-pitch distance used in a particular design. In context of the present disclosure, a poly-pitch distance pp could be a distance between the outer edges of a gate of the gate stack 322 and a gate that would be provided next along the fin (that gate not specifically shown in FIG. 3A in order to not clutter the drawing). Furthermore, in some embodiments, ranges for various distances according to various embodiments of the present disclosure may be expressed in terms of the fin-height fh - e.g. the depth of region 350 may be between 1/10 x fh and 2 x fh including all values and ranges therein, where fh is a fin-height distance used in a particular technology. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g. optical microscopy or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g. Physical Failure Analysis (PFA) would allow determination of the positions of the various regions of different dopant concentrations and types within the semiconductor layer 304 as described herein.

[0072] As described above, the shallow implant region 356 is optional in the FinFET 300. FIGS. 4A- 4C illustrate the FinFET 300 as shown in FIGS. 3A-3C and described above, but illustrating a second embodiment of the present disclosure where the shallow implant region 356 is absent. Except for this difference, other discussions provided above with reference to FIGS. 3A-3C are applicable to the embodiment shown in FIGS. 4A-4C, and, therefore, in the interests of brevity, are not repeated. One advantage of implementing the embodiment as shown in FIGS. 4A-4C include the reduction of band- to-band tunneling of carriers which directly decreases Gate Induced Drain Leakage (GIDL).

Furthermore, embodiment as shown in FIGS. 4A-4C reduces fabrication complexity and

manufacturing costs, by reducing the number of implantation steps compared to embodiment depicted in FIGS.3A-3C.

[0073] In some embodiments, multiple FinFETs similar to the FinFET 300 shown in FIGS. 3A-3C and 4A-4C, as well as multiple regions of modified doping profile associated with the FinFET 300 as described above may be provided along a single fin such as the fin 320, with considerations relevant to providing multiple devices on a single fin being known in the art and, therefore, in the interests of brevity, not specifically described here. In various embodiments, each of the multiple FinFETs provided along a single fin, may be a FinFET according to any one of the embodiments shown in FIGS. 3A-3C and 4A-4C (thus, FinFETs according to different ones of the embodiments shown in FIGS. 3A-3C and 4A-4C may be implemented along a single fin).

[0074] Although particular arrangements of materials are discussed with reference to FIGS. 3A-3C and 4A-4C, intermediate materials may be included in the transistor devices of these FIGS. Note that FIGS. 3A-3C and 4A-4C are intended to show relative arrangements of the components therein, and that transistor devices of these FIGS may include other components that are not illustrated (e.g., gate spacers or various interfacial layers). Additionally, although various components of the transistor devices are illustrated in FIGS. 3A-3C and 4A-4C as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these transistors may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate transistors.

[0075] FinFETs implementing ED concept with modified doping profiles as disclosed herein may be manufactured using any suitable techniques. For example, FIG. 5 is a flow diagram of an example method 500 of manufacturing a FinFET implementing ED concept with a modified doping profile, in accordance with various embodiments. Although the operations of the method 500 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple FinFETs implementing ED concept with modified doping profiles substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a particular FinFET in which a semiconductor layer 304 with a modified doping profile will be included.

[0076] At 502, one or more semiconductor materials for forming a semiconductor/channel layer with modified doping profile where the semiconductor layer has a plurality of regions with different dopant concentrations and/or types, according to any of the embodiments described herein, may be provided. The semiconductor layer provided at 502 may take the form of any of the embodiments of the semiconductor layer 304 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistor 300 illustrated in FIGS. 3A-3C and 4A-4C). The various regions of the semiconductor layer provided at 502 may take the form of any of the embodiments of one or more of the low-doped layer 340, the HD S/D regions 334, 336, the N-well region 344, the P-well region 346, the connection region 350, the low-doped buffer region 348, and the shallow implant 356, described herein.

[0077] The regions with various dopant concentrations/types within the semiconductor layer provided at 502 may be implemented using any suitable manufacturing techniques known in the art. For example, formation of such regions may be achieved by using appropriate mask(s) or/and appropriate spacer(s) for implementing the various regions at desired locations of a future transistor.

[0078] In various embodiments, each of the different regions of the semiconductor layer 304 may be formed using either an implantation/diffusion process or a deposition process. [0079] In the former process, creation of the various regions as described herein may start with providing a base semiconductor layer, e.g. a layer of a low-doped P-type semiconductor material which would form a basis for the semiconductor layer 304, in which various regions with various dopant concentrations and types, as described herein, will later be formed. A layer of the low- doped material 340 as described herein may be used as such a base semiconductor layer for forming various regions of the semiconductor layer 304 for a PMOS transistor as described herein. A thickness of such layer may be equal to or greater than the thickness of the final semiconductor layer with various modified doping profile regions that is being fabricated. Next, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into this initial P-type semiconductor material to form the regions with various dopant concentration and type in the final semiconductor layer 304. An annealing process that activates the dopants and causes them to diffuse farther into the initial P-type semiconductor material may follow the ion implantation process. In some embodiments, such an anneal may be an ultra-fast anneal using laser light or flash annealing which are state of art annealing processes used to reduce Transient Enhanced Diffusion.

[0080] In the latter process, an epitaxial deposition process may provide materials for each of the regions with various dopant concentration and type in the final semiconductor layer 304. In some implementations, at least some of these regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the various regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V materials or alloys. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the highly doped regions such as e.g. the HD source region 334 and/or the HD drain region 336. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the base semiconductor layer, e.g. the initial layer of a low-doped P-type semiconductor material suitable to serve as a base semiconductor layer for forming transistors, in which the materials for the various regions of the modified profiles described herein are deposited.

[0081] At 504, a gate dielectric material may be provided over a first portion of the semiconductor layer with the modified doping profile formed at 502. The gate dielectric material provided at 504 may take the form of any of the embodiments of the gate dielectric material 308 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistor 300). The gate dielectric material may be provided at 504 using any suitable deposition and patterning techniques known in the art. [0082] At 506, the gate, source, and drain electrodes may be provided over the respective portions of the semiconductor layer with the modified doping profile formed at 502. The S/D electrode material provided at 506 may take the form of any of the embodiments of the S/D electrode material 310 disclosed herein while the gate electrode material provided at 506 may take the form of any of the embodiments of the gate electrode material 306 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the transistor 300). The gate, source, and drain electrodes may be provided at 506 using any suitable deposition and patterning techniques known in the art.

[0083] FinFETs implementing ED concept with modified doping profiles disclosed herein may be included in any suitable electronic device. FIGS. 6-9 illustrate various examples of apparatuses that may include one or more of the FinFETs implementing ED concept with modified doping profiles, as disclosed herein.

[0084] FIGS. 6A-6B are top views of a wafer 2000 and dies 2002 that may include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more transistors 300 or any other FinFETs implementing ED concept with modified doping profiles as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more transistors 300 or any other FinFETs implementing ED concept with modified doping profiles as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more FinFETs implementing ED concept with modified doping profiles as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 7, discussed below, which may take the form of any of the FinFETs implementing ED concept with modified doping profiles as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2302 of FIG. 9) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0085] FIG. 7 is a cross-sectional side view of an IC device 2100 that may include one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. The IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 6A) and may be included in a die (e.g., the die 2002 of FIG. 6B). The substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used. The substrate 2102 may be part of a singulated die (e.g., the dies 2002 of FIG. 6B) or a wafer (e.g., the wafer 2000 of FIG. 6A).

[0086] The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal- oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. The S/D regions 2120 of at least some of the transistors 2140 may include the HD source region 334 and the HD drain region 336 as described herein, or any other asymmetric source and drain regions where an HD drain region is positioned as a horizontal/lateral shift with respect to the gate and is not adjacent to the gate. The transistors 2140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 2140 are not limited to the type and configuration depicted in FIG. 7 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Some of the non-planar transistors 2140 may include FinFET transistors, such as e.g. FinFETs 300 described herein. In particular, at least some of the non-planar transistors 2140 may include semiconductor layers with modified doping profiles in accordance with any of the embodiments disclosed herein. For example, such transistors 2140 may take the form of any of the transistors 300 or any other FinFETs implementing ED concept with modified doping profiles disclosed herein. Other non-planar transistors 2140 may include conventional FinFET transistors and wrap-around or all-around gate transistors, such as nano-ribbon and nanowire transistors.

[0087] Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor 2140 may take the form of any of the embodiments of the high-k dielectric 308 disclosed herein, for example.

[0088] In some embodiments, when viewed as a cross-section of the transistor 2140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate (e.g., as illustrated for FinFETs 100, 200, and 300 described herein). In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak).

[0089] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0090] The S/D regions 2120 may be formed within the substrate 2102 and asymmetric with respect to the gate 2122 of at least some of the transistors 2140, as described herein. The S/D regions 2120 formed within the substrate 2102 may take the form of any of the embodiments of the HD source region 334 and the HD drain region 336 discussed above. Furthermore, other regions with varying dopant concentrations and types may be formed within the substrate 2102. Such other regions formed within the substrate 2102 may take the form of any of the embodiments of the low- doped layer 340, the N-well region 344, the P-well region 346, the connection region 350, the low- doped buffer region 348, and the shallow implant 356, discussed above. The S/D regions 2120 and various other regions of the modified doping profile may be formed within the substrate 2102 using any suitable processes known in the art, some of which are described above.

[0091] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 7 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.

[0092] The interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 7). Although a particular number of interconnect layers 2106-2110 is depicted in FIG. 7, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0093] In some embodiments, the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 7. The via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together.

[0094] The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 7. In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.

[0095] A first interconnect layer 2106 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown. The trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

[0096] A second interconnect layer 2108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106. Although the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0097] A third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

[0098] The IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110. The bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices. For example, solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board). The IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments. For example, the bond pads 2136 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

[0099] FIG. 8 is a cross-sectional side view of an IC device assembly 2200 that may include components having one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. The IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard). The IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242. In particular, any suitable ones of the components of the IC device assembly 2200 may include any of the FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. [0100] In some embodiments, the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.

[0101] The IC device assembly 2200 illustrated in FIG. 8 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216. The coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0102] The package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218. The coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 8, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204. The interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220. The IC package 2220 may be or include, for example, a die (the die 2002 of FIG.6B), an IC device (e.g., the IC device 2100 of FIG. 7), or any other suitable component. Generally, the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202. In the embodiment illustrated in FIG. 8, the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204. In some

embodiments, three or more components may be interconnected by way of the interposer 2204.

[0103] The interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206. The interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2204. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.

[0104] The IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222. The coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216, and the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.

[0105] The IC device assembly 2200 illustrated in FIG. 8 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228. The package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232. The coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.

[0106] FIG. 9 is a block diagram of an example computing device 2300 that may include one or more components including one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 6B)) having one or more FinFETs implementing ED concept with modified doping profiles in accordance with any of the embodiments disclosed herein. Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 7). Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 8).

[0107] A number of components are illustrated in FIG. 9 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. [0108] Additionally, in various embodiments, the computing device 2300 may not include one or more of the components illustrated in FIG. 9, but the computing device 2300 may include interface circuitry for coupling to the one or more components. For example, the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled. In another set of examples, the computing device 2300 may not include an audio input device 2318 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2318 or audio output device 2308 may be coupled.

[0109] The computing device 2300 may include a processing device 2302 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-M RAM).

[0110] In some embodiments, the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips). For example, the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0111] The communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (I EEE) standards including Wi-Fi (IEEE 802.11 family), I EEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2312 may operate in accordance with other wireless protocols in other embodiments. The computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0112] In some embodiments, the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2312 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.

[0113] The computing device 2300 may include battery/power circuitry 2314. The battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).

[0114] The computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above). The display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0115] The computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above). The audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0116] The computing device 2300 may include an audio input device 2318 (or corresponding interface circuitry, as discussed above). The audio input device 2318 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).

[0117] The computing device 2300 may include a GPS device 2316 (or corresponding interface circuitry, as discussed above). The GPS device 2316 may be in communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.

[0118] The computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0119] The computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0120] The computing device 2300 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2300 may be any other electronic device that processes data.

[0121] The following paragraphs provide various examples of the embodiments disclosed herein.

[0122] Example 1 provides a transistor channel layer arrangement for a P-type metal-oxide- semiconductor (PMOS) field-effect transistor (Fin FET) that includes a semiconductor layer (e.g. the semiconductor layer 304) formed of one or more semiconductor materials and having a plurality of regions with different dopant concentrations. The plurality of regions include an N-well region (e.g. the N-well region 344) (i.e. a region of one or more semiconductor materials doped with N-type dopants), a P-well region (e.g. the P-well region 346) including one or more P-type regions (i.e. regions of one or more semiconductor materials doped with P-type dopants), a low-doped buffer region (e.g. the low-doped buffer region 348) between (i.e. separating) the P-well region and the N- well region, the low-doped buffer region including P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and a connection region (e.g. the connection region/layer 350) provided over the low-doped buffer region, between the P-well region and the N- well region (i.e. the connection region connects the P-well region and the N-well region, i.e. one end of the connection region is in contact with a portion of the P-well region and another end of the connection region is in contact with a portion of the N-well region), the connection region including P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region, e.g. the dopant concentration of the low-doped buffer region may be about 0.2%- 1.0% of the dopant concentration of the connection region.

[0123] Example 2 provides the transistor channel layer arrangement according to Example 1, where the semiconductor layer is shaped as a fin, the fin including an active fin portion and a sub-fin portion. In a FinFET transistor including such a transistor channel arrangement, a gate electrode stack would wrap around the active fin portion of the fin. Namely, the high-k gate dielectric of the gate electrode stack would wrap around the active fin portion of the fin and the gate electrode material would wrap around the high-k gate dielectric, with the sub-fin portion of the fin being enclosed by the low-k dielectric material (e.g. STI).

[0124] Example 3 provides the transistor channel layer arrangement according to Example 2, where a thickness of the connection region (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height of the active fin portion of the fin.

[0125] Example 4 provides the transistor channel layer arrangement according to Example 1, where the one or more P-type regions of the P-well region include a highly doped (HD) drain region not adjacent to the gate electrode stack and electrically connected to a drain electrode, and a shallow implant region (e.g. the shallow implant 356, also referred to as an upper P-type region) between the connection region and the HD drain region (i.e. the shallow implant connects the connection region and the HD drain region of the P-well region, i.e. one end of the shallow implant is in contact with the connection region and another end of the shallow implant is in contact with the HD drain region; thus the connection region is connected to the HD drain region via the shallow implant).

[0126] Example 5 provides the transistor channel layer arrangement according to Example 4, where a dopant concentration of the shallow implant is higher than the dopant concentration of the connection region, e.g. the dopant concentration of the connection region may be about 10%- 50% of the dopant concentration of the shallow implant.

[0127] Example 6 provides the transistor channel layer arrangement according to Examples 4 or 5, where a dopant concentration of the shallow implant is lower than a dopant concentration of the HD drain region, e.g. the dopant concentration of the shallow implant may be about 0.2%-1.0% of the dopant concentration of the HD drain region. Thus, the HD drain region may be the P-type region with the highest dopant concentration in said semiconductor layer (together with the HD source region on the other side of the gate stack), the shallow implant is the P-type region with the next-highest P-type dopant concentration (the dopant concentration of the P-well region below the shallow implant may be about the same or lower than that of the shallow implant but higher than that of the low-doped buffer region), followed by either the connection region or the part of the P- well below the shallow implant having the P-type dopants with the next-highest concentration after the shallow implant, and the low-doped buffer region has the lowest P-type dopant concentration.

[0128] Example 7 provides the transistor channel layer arrangement according to any one of Examples 4-6, where the semiconductor layer is shaped as a fin, the fin including an active fin portion and a sub-fin portion. Similar to Example 2 above, in a FinFET transistor including such a transistor channel arrangement, a gate electrode stack would wrap around the active fin portion of the fin. Namely, the high-k gate dielectric of the gate electrode stack would wrap around the active fin portion of the fin and the gate electrode material would wrap around the high-k gate dielectric, with the sub-fin portion of the fin being enclosed by the low-k dielectric material (e.g. STI).

[0129] Example 8 provides the transistor channel layer arrangement according to Example 7, where a thickness of the shallow implant (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height (also measured in the direction of the z-axis shown in the FIGS.) of the active fin portion of the fin.

[0130] Example 9 provides the transistor channel layer arrangement according to Examples 7 or 8, where a thickness of the connection region (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height of the active fin portion of the fin.

[0131] Example 10 provides the transistor channel layer arrangement according to any one of Examples 4-9, where a first portion of the shallow implant region is in contact with a portion of the connection region.

[0132] Example 11 provides the transistor channel layer arrangement according to any one of Examples 4-10, where a second portion of the shallow implant region is in contact with a portion of the HD drain region. [0133] Example 12 provides the transistor channel layer arrangement according to any one of the preceding Examples, where the connection region is an uppermost layer in a portion of the semiconductor layer.

[0134] Example 13 provides the transistor channel layer arrangement according to any one of the preceding Examples, further including a gate electrode stack provided over a portion of the semiconductor layer, the gate electrode stack including a gate dielectric material and a gate electrode material, where the gate dielectric material is between the gate electrode material and the portion of the semiconductor layer.

[0135] Example 14 provides a method of manufacturing a transistor structure. The method includes providing a semiconductor layer according to any one of the preceding Examples, the semiconductor layer including one or more semiconductor materials and having a plurality of regions with different dopant concentrations; providing a gate electrode stack over a first portion of the semiconductor layer; and providing a source electrode and a drain electrode over portions of the semiconductor layer at different sides of the gate electrode stack. The plurality of regions include an N-well region, a P-well region including one or more P-type regions, a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region including P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region including P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region.

[0136] Example 15 provides the method according to Example 14, where providing the plurality of regions with different dopant concentrations includes performing ion dopant implantation on the one or more semiconductor materials of the semiconductor layer.

[0137] Example 16 provides the method according to Example 15, further including performing an anneal of the transistor structure to activate dopants provided by the ion dopant implantation.

[0138] Example 17 provides the method according to Example 14, where providing the plurality of regions with different dopant concentrations includes forming one or more openings in the one or more semiconductor materials of the semiconductor layer, and depositing one or more doped semiconductor materials into the one or more openings to form the plurality of regions with different dopant concentrations.

[0139] Example 18 provides the method according to Example 17, where the one or more doped semiconductor materials are deposited into the one or more openings by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). [0140] Example 19 provides a transistor structure that includes a semiconductor layer (e.g. the semiconductor layer 304) including one or more semiconductor materials and having a plurality of regions with different dopant concentration; a drain electrode provided over the HD drain region; and a gate electrode stack provided over a portion of the semiconductor layer that is not adjacent to the HD drain region (in other words, the HD drain region is horizontally/laterally shifted away from the gate stack, with at least the connection region separating the portion of the semiconductor layer under the gate stack and the HD drain region). The plurality of regions include an N-well region, a P- well region including one or more P-type regions, the one or more P-type regions including a highly doped (HD) drain region, a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region including P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region including P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region.

[0141] Example 20 provides the transistor structure according to Example 19, where the portion of the semiconductor layer under the gate electrode stack includes a portion of the connection region

(i.e. the connection region connects to the N-well region under the gate electrode stack).

[0142] Example 21 provides the transistor structure according to Example 19, where the portion of the semiconductor layer under the gate electrode stack is in contact with a portion of the connection region (i.e. the connection region connects to the N-well region at the edge of the gate electrode stack, e.g. at the edge aligned with the point 360 shown in FIG. 3A).

[0143] Example 22 provides the transistor structure according to any one of Examples 19-21, where the gate electrode stack includes a gate dielectric material and a gate electrode material, where the gate dielectric material is between the gate electrode material and the portion of the semiconductor layer.

[0144] Example 23 provides the transistor structure according to any one of Examples 19-22, where the plurality of regions of the semiconductor layer further includes a HD source region, and the transistor structure further includes a source electrode provided over the HD source region.

[0145] Example 24 provides the transistor structure according to Example 23, where at least a portion of the HD source region is in contact with the N-well region.

[0146] Example 25 provides the transistor structure according to Examples 23 or 24, where the HD source region includes P-type dopants.

[0147] Example 26 provides the transistor structure according to any one of Examples 19-25, where the N-well region includes N-type dopants. [0148] Example 27 provides the transistor structure according to any one of Examples 19-26, where the semiconductor layer is shaped as a fin, the fin including an active fin portion and a sub-fin portion.

[0149] Example 28 provides the transistor structure according to Example 27, where a thickness of the connection region (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height of the active fin portion of the fin.

[0150] Example 29 provides the transistor structure according to any one of Examples 19-26, where the one or more P-type regions of the P-well region include a shallow implant region (e.g. the shallow implant 356) between the connection region and the H D drain region.

[0151] Example 30 provides the transistor structure according to Example 29, where a dopant concentration of the shallow implant is higher than the dopant concentration of the connection region, similar to Example 5 described above.

[0152] Example 31 provides the transistor structure according to Examples 29 or 30, where a dopant concentration of the shallow implant is lower than a dopant concentration of the H D drain region, similar to Example 6 described above.

[0153] Example 32 provides the transistor structure according to any one of Examples 29-31, where the semiconductor layer is shaped as a fin, the fin including an active fin portion and a sub-fin portion, similar to Example 2 described above.

[0154] Example 33 provides the transistor structure according to Example 32, where a thickness of the shallow implant (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height (also measured in the direction of the z-axis shown in the FIGS.) of the active fin portion of the fin.

[0155] Example 34 provides the transistor structure according to Examples 32 or 33, where a thickness of the connection region (measured in the direction of the z-axis shown in the FIGS.) is between 5% and 100% of a height of the active fin portion of the fin.

[0156] Example 35 provides the transistor structure according to any one of Examples 29-34, where a first portion of the shallow implant region is in contact with a portion of the connection region.

[0157] Example 36 provides the transistor structure according to any one of Examples 29-35, where a second portion of the shallow implant region is in contact with a portion of the H D drain region.

[0158] Example 37 provides the transistor structure according to any one of Examples 19-36, where the connection region is an uppermost layer in a portion of the semiconductor layer.

[0159] Example 38 provides a computing device that includes a substrate and an integrated circuit (IC) die coupled to the substrate. The IC die includes a P-type metal-oxide-semiconductor (PMOS) field-effect transistor (FinFET) structure including a semiconductor layer (e.g. the semiconductor layer 304) including one or more semiconductor materials and having a plurality of regions with different dopant concentrations, where the plurality of regions include an N-well region, a P-well region including one or more P-type regions, the one or more P-type regions including a highly doped (H D) drain region, a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region including P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region including P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region.

[0160] In various other Examples, the PMOS FinFET structure of Example 38 may be/include a transistor structure according to any one of Examples 19-37.

[0161] Example 39 provides the computing device according to Example 38, where the computing device is a wearable or handheld computing device.

[0162] Example 40 provides the computing device according to Examples 38 or 39, where the computing device further includes one or more communication chips and an antenna.

[0163] Example 41 provides the computing device according to any one of Examples 38-40, where the substrate is a motherboard.

[0164] While embodiments of the present disclosure are explained with reference to PMOS transistors implementing the low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region comprising P-type dopants with a dopant concentration less than that of the P-well region, descriptions provided herein are equally applicable to embodiments of PMOS transistors implementing the low-doped buffer region having N-type dopants with a dopant concentration less than that of any N-type regions within an N-well region as described herein. Furthermore, descriptions provided herein are equally applicable to embodiments of PMOS transistors where the low-doped buffer region having P-type of N-type dopants as described above is replaced with a substantially intrinsic semiconductor material (i.e. material that is not intentionally doped). In all of these cases, as long as a dopant concentration of what may now simply be called a "buffer region" (which could be either a low-doped buffer region with P-type or N-type dopants, or be a substantially undoped semiconductor) is less than each of a dopant concentration of any of the regions within the P-well region, a dopant concentration of any of the regions within the N-well region, and a dopant concentration of the connection region of a PMOS transistor, advantages of suppression of the current leakage as described herein may still be realized. Providing the buffer region which has a low dopant concentration (i.e. which may be a low-doped extrinsic

semiconductor material or a substantially intrinsic semiconductor material) and, therefore, has low conductivity for the charge carriers of the current in the ON and OFF states of a PMOS transistor (e.g. a P-type FinFET), together with a P-type semiconductor of the connection region (i.e. a region which is conductive for the charge carriers of the current in the ON and OFF states of a PMOS transistor), may ensure that the current flow in the ON and OFF states of the transistor is contained substantially in the connection region. Providing the connection region substantially in the active fin portion of a fin into which the semiconductor layer with such a modified doping profile is shaped may ensure that the current flow is substantially contained in the high-quality active fin portion of a fin, avoiding the bad quality sub-fin region. As a result, a transistor can be more robust against trap- induced drain leakage and the leakage current may be significantly reduced (e.g. reduced by several orders of magnitude).

[0165] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0166] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims:

1. A transistor channel layer arrangement, comprising:

a semiconductor layer for a P-type metal-oxide-semiconductor (PMOS) field-effect transistor (FinFET), the semiconductor layer having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region,

a P-well region comprising one or more P-type regions,

a low-doped buffer region between the P-well region and the N-well region, the low-doped buffer region comprising P-type dopants with a dopant concentration less than that of any of the one or more P-type regions, and

a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region.

2. The transistor channel layer arrangement according to claim 1, wherein the semiconductor layer is shaped as a fin, the fin comprising an active fin portion and a sub-fin portion.

3. The transistor channel layer arrangement according to claim 2, wherein a thickness of the connection region is between 5% and 100% of a height of the active fin portion of the fin.

4. The transistor channel layer arrangement according to claim 1, wherein the one or more P-type regions include a highly doped (HD) drain region, and a shallow implant between the connection region and the HD drain region.

5. The transistor channel layer arrangement according to claim 4, wherein a dopant concentration of the shallow implant is higher than the dopant concentration of the connection region.

6. The transistor channel layer arrangement according to claim 4, wherein a dopant concentration of the shallow implant is lower than a dopant concentration of the HD drain region.

7. The transistor channel layer arrangement according to claim 4, wherein the semiconductor layer is shaped as a fin, the fin comprising an active fin portion and a sub-fin portion.

8. The transistor channel layer arrangement according to claim 7, wherein a thickness of the shallow implant is between 5% and 100% of a height of the active fin portion of the fin.

9. The transistor channel layer arrangement according to claim 7, wherein a thickness of the connection region is between 5% and 100% of a height of the active fin portion of the fin.

10. The transistor channel layer arrangement according to any one of claims 4-9, wherein a first portion of the shallow implant region is in contact with a portion of the connection region.

11. The transistor channel layer arrangement according to any one of claims 4-9, wherein a second portion of the shallow implant region is in contact with a portion of the HD drain region.

12. The transistor channel layer arrangement according to any one of claims 1-9, wherein the connection region is an uppermost layer in the semiconductor layer.

13. The transistor channel layer arrangement according to any one of claims 1-9, further comprising a gate electrode stack over a portion of the semiconductor layer, the gate electrode stack comprising a gate dielectric material and a gate electrode material, where the gate dielectric material is between the gate electrode material and the portion of the semiconductor layer.

14. A method of manufacturing a transistor structure, the method comprising:

providing a semiconductor layer comprising one or more semiconductor materials and having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region,

a P-well region comprising one or more P-type regions,

a connection region over the low-doped buffer region, between the P-well region and the N-well region, the connection region comprising P-type dopants with a dopant concentration higher than the dopant concentration of the low-doped buffer region;

providing a gate electrode stack over a first portion of the semiconductor layer;

providing a source electrode and a drain electrode over portions of the semiconductor layer at different sides of the gate electrode stack.

15. The method according to claim 14, wherein providing the plurality of regions with different dopant concentrations comprises performing ion dopant implantation on the one or more semiconductor materials of the semiconductor layer.

16. The method according to claim 15, further comprising performing an anneal of the transistor structure to activate dopants provided by the ion dopant implantation.

17. The method according to claim 14, wherein providing the plurality of regions with different dopant concentrations comprises:

forming one or more openings in the one or more semiconductor materials of the semiconductor layer, and

depositing one or more doped semiconductor materials into the one or more openings to form the plurality of regions with different dopant concentrations.

18. The method according to claim 17, wherein the one or more doped semiconductor materials are deposited into the one or more openings by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

19. A transistor structure comprising:

a semiconductor layer comprising one or more semiconductor materials and having a plurality of regions with different dopant concentrations, the plurality of regions comprising:

an N-well region,

a P-well region comprising one or more P-type regions, the one or more P-type regions comprising a highly doped (HD) drain region,

a drain electrode over the HD drain region; and

a gate electrode stack over a portion of the semiconductor layer that is not adjacent to the HD drain region.

20. The transistor structure according to claim 19, wherein the portion of the semiconductor layer under the gate electrode stack comprises a portion of the connection region.

21. The transistor structure according to claim 19, wherein the portion of the semiconductor layer under the gate electrode stack is in contact with a portion of the connection region.

22. The transistor structure according to any one of claims 19-21, wherein the gate electrode stack comprises a gate dielectric material and a gate electrode material, where the gate dielectric material is between the gate electrode material and the portion of the semiconductor layer.

23. The transistor structure according to any one of claims 19-21, wherein the plurality of regions further comprises a HD source region, and the transistor structure further comprises a source electrode over the HD source region.

24. The transistor structure according to claim 23, wherein at least a portion of the HD source region is in contact with the N-well region.

25. The transistor structure according to any one of claims 19-21, wherein the semiconductor layer is shaped as a fin, the fin comprising an active fin portion and a sub-fin portion.