JP2008505482A5 - - Google Patents

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Publication number
JP2008505482A5
JP2008505482A5 JP2007519189A JP2007519189A JP2008505482A5 JP 2008505482 A5 JP2008505482 A5 JP 2008505482A5 JP 2007519189 A JP2007519189 A JP 2007519189A JP 2007519189 A JP2007519189 A JP 2007519189A JP 2008505482 A5 JP2008505482 A5 JP 2008505482A5
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JP
Japan
Prior art keywords
layer
relaxed
concentration
strained
sige
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007519189A
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English (en)
Japanese (ja)
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JP2008505482A (ja
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Publication date
Priority claimed from US10/710,255 external-priority patent/US6893936B1/en
Application filed filed Critical
Publication of JP2008505482A publication Critical patent/JP2008505482A/ja
Publication of JP2008505482A5 publication Critical patent/JP2008505482A5/ja
Pending legal-status Critical Current

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JP2007519189A 2004-06-29 2005-02-16 シリコン・ゲルマニウム・バッファで絶縁体上に歪みSi/SiGeを形成する方法 Pending JP2008505482A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/710,255 US6893936B1 (en) 2004-06-29 2004-06-29 Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
PCT/US2005/005085 WO2006011912A1 (en) 2004-06-29 2005-02-16 Method of forming strained si/sige on insulator with silicon germanium buffer

Publications (2)

Publication Number Publication Date
JP2008505482A JP2008505482A (ja) 2008-02-21
JP2008505482A5 true JP2008505482A5 (cg-RX-API-DMAC7.html) 2008-04-03

Family

ID=34573464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007519189A Pending JP2008505482A (ja) 2004-06-29 2005-02-16 シリコン・ゲルマニウム・バッファで絶縁体上に歪みSi/SiGeを形成する方法

Country Status (7)

Country Link
US (1) US6893936B1 (cg-RX-API-DMAC7.html)
EP (1) EP1779422A4 (cg-RX-API-DMAC7.html)
JP (1) JP2008505482A (cg-RX-API-DMAC7.html)
KR (1) KR20070032649A (cg-RX-API-DMAC7.html)
CN (1) CN1954421A (cg-RX-API-DMAC7.html)
TW (1) TWI348200B (cg-RX-API-DMAC7.html)
WO (1) WO2006011912A1 (cg-RX-API-DMAC7.html)

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DE102006019934B4 (de) 2006-04-28 2009-10-29 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Ausbildung eines Feldeffekttransistors
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FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
CN100447950C (zh) * 2007-01-26 2008-12-31 厦门大学 低位错密度锗硅虚衬底的制备方法
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
JP5747401B2 (ja) 2009-09-04 2015-07-15 住友化学株式会社 半導体基板、電界効果トランジスタ、集積回路、及び半導体基板の製造方法
CN101882624B (zh) 2010-06-29 2011-09-14 清华大学 在绝缘衬底上形成有高Ge应变层的结构及形成方法
CN102315246B (zh) * 2010-06-30 2013-03-13 中国科学院上海硅酸盐研究所 一种弛豫SiGe虚拟衬底及其制备方法
RU2014107762A (ru) * 2011-08-01 2015-09-10 Басф Се СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВЫХ УСТРОЙСТВ, ВКЛЮЧАЮЩИЙ ХИМИКО-МЕХАНИЧЕСКОЕ ПОЛИРОВАНИЕ ЭЛЕМЕНТАРНОГО ГЕРМАНИЯ И/ИЛИ МАТЕРИАЛА НА ОСНОВЕ Si1-xGex В ПРИСУТСТВИИ ХМП КОМПОЗИЦИИ, ОБЛАДАЮЩЕЙ ЗНАЧЕНИЕМ pH ОТ 3,0 ДО 5,5
CN102427068B (zh) * 2011-12-02 2014-06-18 中国科学院上海微系统与信息技术研究所 单片集成具有晶格失配的晶体模板及其制作方法
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
CN103165511B (zh) * 2011-12-14 2015-07-22 中国科学院上海微系统与信息技术研究所 一种制备goi的方法
TWI457985B (zh) * 2011-12-22 2014-10-21 Nat Inst Chung Shan Science & Technology Semiconductor structure with stress absorbing buffer layer and manufacturing method thereof
US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
KR101381056B1 (ko) * 2012-11-29 2014-04-14 주식회사 시지트로닉스 Ⅲ-질화계 에피층이 성장된 반도체 기판 및 그 방법
US9716176B2 (en) * 2013-11-26 2017-07-25 Samsung Electronics Co., Ltd. FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same
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KR102257423B1 (ko) 2015-01-23 2021-05-31 삼성전자주식회사 반도체 기판 및 이를 포함하는 반도체 장치
US10304722B2 (en) 2015-06-01 2019-05-28 Globalwafers Co., Ltd. Method of manufacturing semiconductor-on-insulator
CN114000121B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于mbe法的应变金刚石生长掺杂方法及外延结构
CN114000120B (zh) * 2022-01-05 2022-03-15 武汉大学 一种基于cvd法的应变金刚石生长掺杂方法
JP2025168976A (ja) * 2024-04-30 2025-11-12 信越半導体株式会社 SiGe基板の作製方法及びSiGe基板

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FR2842349B1 (fr) * 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
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FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
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