JP2008282499A - 不揮発性メモリ装置及びそのデータ書き込み方法 - Google Patents
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- 150000004706 metal oxides Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
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- 239000002184 metal Substances 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- G—PHYSICS
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G11C13/004—Reading or sensing circuits or methods
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
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- G11C—STATIC STORES
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
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Abstract
【解決手段】互いに交差する第1の配線と第2の配線及び、それらの各交差部に配置された、電気的書き換え可能な抵抗値をデータとして不揮発に記憶する可変抵抗素子と整流素子を直列接続したメモリセルとを有する不揮発性メモリ装置のデータ書き込み方法であって、選択された第1の配線の立ち上げに先立って、全ての第2の配線を各メモリセルの整流素子が逆バイアスとなるように整流素子のしきい値以上の所定電圧に充電し、前記選択された第1の配線を書き込み又は消去に必要な電圧に充電した後、選択された第2の配線を放電させる。
【選択図】図5
Description
選択された第1の配線の立ち上げに先立って、全ての第2の配線を各メモリセルの整流素子が逆バイアスとなるように整流素子のしきい値以上の所定電圧に充電し、
前記選択された第1の配線を書き込み又は消去に必要な電圧に充電した後、
選択された第2の配線を放電させることを特徴とする。
前記ビット線に接続されるセンスユニットとを有し、
前記センスユニットは、
前記メモリセルのデータをセンスするセンスアンプと、
前記ビット線を直接所定電位のノードに接続するための第1の電流経路と、
前記ビット線を抵抗を介して前記所定電位のノードに接続するための第2の電流経路と、
書き込みデータに応じて前記第1及び第2の電流経路を選択的にオンする制御を行うデータ処理回路と、を有することを特徴とする。
Claims (5)
- 互いに交差する第1の配線と第2の配線及び、それらの各交差部に配置された、電気的書き換え可能な抵抗値をデータとして不揮発に記憶する可変抵抗素子と整流素子を直列接続したメモリセルとを有する不揮発性メモリ装置のデータ書き込み方法であって、
選択された第1の配線の立ち上げに先立って、全ての第2の配線を各メモリセルの整流素子が逆バイアスとなるように整流素子のしきい値以上の所定電圧に充電し、
前記選択された第1の配線を書き込み又は消去に必要な電圧に充電した後、
選択された第2の配線を放電させる
ことを特徴とする不揮発性メモリ装置のデータ書き込み方法。 - 第1の配線がワード線、第2の配線がビット線であって、ワード線がビット線に対して正バイアスのとき整流素子が順バイアスとなるようにメモリセルがワード線とビット線に接続され、
データ書き込み時、選択ワード線の立ち上げに先立って、全てのビット線を各メモリセルが逆バイアスとなるように整流素子のしきい値以上の所定電圧に充電し、
前記選択ワード線を書き込み又は消去に必要な電圧に充電した後、選択ビット線を直接接地して放電させることにより、可変抵抗素子を低抵抗状態から高抵抗状態へ遷移させ、前記選択ビット線を抵抗を介して接地して放電させることにより、可変抵抗素子を高抵抗状態から低抵抗状態へ遷移させる
ことを特徴とする請求項1記載の不揮発性メモリ装置のデータ書き込み方法。 - 第1の配線がビット線、第2の配線がワード線であって、ビット線がワード線に対して正バイアスのとき整流素子が順バイアスとなるようにメモリセルがワード線とビット線に接続され、
データ書き込み時、選択ビット線の立ち上げに先立って、全てのワード線を各メモリセルが逆バイアスとなるように整流素子のしきい値以上の所定電圧に充電し、
前記選択ビット線を書き込み又は消去に必要な電圧に充電した後、選択ワード線を直接接地して放電させることにより、可変抵抗素子を低抵抗状態から高抵抗状態へ遷移させ、前記選択ワード線を抵抗を介して接地して放電させることにより、可変抵抗素子を高抵抗状態から低抵抗状態へ遷移させる
ことを特徴とする請求項1記載の不揮発性メモリ装置のデータ書き込み方法。 - 互いに交差するワード線とビット線の交差部に配置された電気的書き換え可能な抵抗値をデータとして不揮発に記憶する可変抵抗素子と整流素子を直列接続したメモリセルと、
前記ビット線に接続されるセンスユニットとを有し、
前記センスユニットは、
前記メモリセルのデータをセンスするセンスアンプと、
前記ビット線を直接所定電位のノードに接続するための第1の電流経路と、
前記ビット線を抵抗を介して前記所定電位のノードに接続するための第2の電流経路と、
書き込みデータに応じて前記第1及び第2の電流経路を選択的にオンする制御を行うデータ処理回路と、
を有することを特徴とする不揮発性メモリ装置。 - 前記センスユニットは、前記センスアンプのセンスノードに接続された書き込み禁止回路を更に備え、
選択メモリセルのデータ書き込み時、書き込みに先立って前記メモリセルのデータを読み出しが行われ、
前記データ処理回路は、読み出しデータと書き込みデータの一致を検出したとき前記書き込み禁止回路をオンにして、前記メモリセルを書き込み禁止状態に設定し、読み出しデータと書き込みデータの不一致を検出したときは書き込みデータに応じて前記第1及び第2の電流経路の一方をオンにして前記メモリセルを書き込み又は消去動作状態に設定する
ことを特徴とする請求項4記載の不揮発性メモリ装置。
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JP2007127090A JP4410272B2 (ja) | 2007-05-11 | 2007-05-11 | 不揮発性メモリ装置及びそのデータ書き込み方法 |
US12/118,064 US7889537B2 (en) | 2007-05-11 | 2008-05-09 | Non-volatile memory device and method for writing data thereto |
US13/005,582 US8000155B2 (en) | 2007-05-11 | 2011-01-13 | Non-volatile memory device and method for writing data thereto |
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JP2010287789A (ja) * | 2009-06-12 | 2010-12-24 | Toshiba Corp | 抵抗変化メモリ |
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JP2011028799A (ja) * | 2009-07-23 | 2011-02-10 | Toshiba Corp | 抵抗変化メモリのテスト装置、方法および抵抗変化メモリ装置 |
US8279655B2 (en) | 2010-02-15 | 2012-10-02 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device |
JP2011204291A (ja) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8264867B2 (en) | 2010-03-24 | 2012-09-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor storage device |
JP2012198968A (ja) * | 2011-03-22 | 2012-10-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
WO2023034709A1 (en) * | 2021-08-31 | 2023-03-09 | Micron Technology, Inc. | Termination for pulse amplitude modulation |
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US20110103135A1 (en) | 2011-05-05 |
US8000155B2 (en) | 2011-08-16 |
JP4410272B2 (ja) | 2010-02-03 |
US20090052227A1 (en) | 2009-02-26 |
US7889537B2 (en) | 2011-02-15 |
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