JP2008171839A - メモリシステム、半導体記憶装置及びその駆動方法 - Google Patents
メモリシステム、半導体記憶装置及びその駆動方法 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
Abstract
【解決手段】半導体基板1上に形成された下部選択トランジスタ2と、下部選択トランジスタ2上に前記半導体基板表面に対し垂直方向に延在する複数のメモリセルトランジスタ3と、メモリセルトランジスタ3上に形成されたダミートランジスタ4と、ダミートランジスタ4上に形成された上部選択トランジスタ5と、を備え、データ書き込み動作時は、下部選択トランジスタ2のゲート電極と最下層のメモリセルトランジスタ3aのゲート電極にはオフレベルの電位が与えられ、上部選択トランジスタ5のゲート電極とダミートランジスタ4のゲート電極には電位Vsgが与えられる。
【選択図】図1
Description
2 下部選択トランジスタ
3 メモリアレイ
4 ダミートランジスタ
5 上部選択トランジスタ
Claims (5)
- 半導体基板と、
前記半導体基板の表面部分に形成された第1の選択トランジスタと、
前記第1の選択トランジスタ上に前記半導体基板表面に対し垂直方向に延在するように形成された複数のメモリセルトランジスタと、
前記メモリセルトランジスタ上に形成されたダミートランジスタと、
前記ダミートランジスタ上に形成された第2の選択トランジスタと、
を備え、
前記メモリセルトランジスタへのデータ書き込み動作時は、前記第1の選択トランジスタのゲート電極と前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極には第1の電位が与えられ、前記第2の選択トランジスタのゲート電極と前記ダミートランジスタのゲート電極に第2の電位が与えられることを特徴とする半導体記憶装置。 - 前記第1の選択トランジスタのドレイン及び前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのソース並びに前記第2の選択トランジスタのソース及び前記ダミートランジスタのドレインの不純物濃度は、前記ダミートランジスタのソース及び前記ダミートランジスタに隣接する前記メモリセルトランジスタのドレインの不純物濃度よりも高いことを特徴とする請求項1記載の半導体記憶装置。
- 半導体基板と、前記半導体基板の表面部分に形成された第1の選択トランジスタと、前記第1の選択トランジスタ上に前記半導体基板表面に対し垂直方向に延在するように形成された複数のメモリセルトランジスタと、前記メモリセルトランジスタ上に形成されたダミートランジスタと、前記ダミートランジスタ上に形成された第2の選択トランジスタと、を備えた半導体記憶装置の駆動方法であって、
データ書き込み時は前記第1の選択トランジスタのゲート電極と前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極に第1の電位を与え、前記第2の選択トランジスタのゲート電極と前記ダミートランジスタのゲート電極に第2の電位を与えることを特徴とする半導体記憶装置の駆動方法。 - データ消去時は前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極及び前記ダミートランジスタのゲート電極をフローティング電位とすることを特徴とする請求項3記載の半導体記憶装置の駆動方法。
- 半導体基板と、前記半導体基板表面部分に形成された第1の選択トランジスタと、前記第1の選択トランジスタ上に前記半導体基板表面に対し垂直方向に延在するように形成された複数のメモリセルトランジスタと、前記メモリセルトランジスタ上に形成されたダミートランジスタと、前記ダミートランジスタ上に形成された第2の選択トランジスタと、を有する記憶部と、
前記複数のメモリセルトランジスタのうち、前記第1の選択トランジスタに隣接する前記メモリセルトランジスタ以外の前記メモリセルトランジスタのゲート電極に電圧を印加するワード線ドライバと、
前記第1の選択トランジスタのゲート電極及び前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極に接続され、前記ワード線ドライバに接続された前記メモリセルトランジスタのデータ書き込み動作時は前記第1の選択トランジスタのゲート電極及び前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極に同電位を与え、前記ワード線ドライバに接続された前記メモリセルトランジスタのデータ消去動作時は前記第1の選択トランジスタに隣接する前記メモリセルトランジスタのゲート電極をフローティング電位にするドライバと、
前記第2の選択トランジスタのゲート電極及び前記ダミートランジスタのゲート電極に接続され、前記ワード線ドライバに接続された前記メモリセルトランジスタのデータ書き込み動作時は前記第2の選択トランジスタのゲート電極及び前記トランジスタのゲート電極に同電位を与え、前記ワード線ドライバに接続された前記メモリセルトランジスタのデータ消去動作時は前記ダミートランジスタのゲート電極をフローティング電位にするセレクトゲートドライバと、
を備えることを特徴とするメモリシステム。
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