JP2008160141A - 集積回路デバイスとその製造方法 - Google Patents
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Abstract
【解決手段】少なくとも一つのマイクロ電子デバイス150に電気的に接触する導電性相互接続部を備える第1の層と、第1の層のラインに対して直角に整列された導電性のラインを備える第2の層であってかつ第2の層のラインが第1の層のラインと電気的に接触している第2の層と、第2の層のラインに対して直角に整列された導電性のラインを備える第3の層であってかつ第3の層のラインが第2の層のラインと電気的に接触している第3の層とを備え、第1の層を第2の層に相互接続し、かつ第3の層を第2の層に相互接続する複数のバイア224等を備える。
【選択図】図2
Description
少なくとも一つのマイクロ電子デバイスと電気的に接触する導電性相互接続部を備える第1の層と、前記第1の層のラインに対して直角に整列された導電性のラインを備える第2の層であって、前記第2の層のラインが、前記第1の層のラインと電気的に接触している第2の層と、前記第2の層のラインに対して直角に整列された導電性のラインを備える第3の層であって、前記第3の層のラインが、前記第2の層のラインと電気的に接触している第3の層と、前記第1の層を前記第2の層に相互接続し、且つ前記第3の層を前記第2の層に相互接続する複数のバイアと、を備える。
120 結合層
150 マイクロ電子デバイス
160 電気コンタクト
130 結合パッド
220,230,240,250 相互接続層
Claims (12)
- 基板と、
前記基板上に配置された、パターン化された特徴部を各々が備え、該パターン化された特徴部が少なくとも一つの電気コンタクトを備える複数のマイクロ電子デバイスと、
前記複数のマイクロ電子デバイスに電力を分配するための複数の相互接続層であって、該相互接続層が各々複数の導電性部材を備え、少なくとも一つの連続する相互接続層の前記導電性部材が、少なくとも一つの他の相互接続層の前記導電性部材に跨っている相互接続層と、
前記相互接続層の複数の前記導電性部材の少なくとも一つに接続する複数の結合パッドと、を備え、
少なくとも一つのマイクロ電子デバイスと電気的に接触する導電性相互接続部を備える第1の層と、
前記第1の層のラインに対して直角に整列された導電性のラインを備える第2の層であって、前記第2の層のラインが、前記第1の層のラインと電気的に接触している第2の層と、
前記第2の層のラインに対して直角に整列された導電性のラインを備える第3の層であって、前記第3の層のラインが、前記第2の層のラインと電気的に接触している第3の層と、
前記第1の層を前記第2の層に相互接続し、且つ前記第3の層を前記第2の層に相互接続する複数のバイアと、を備えたことを特徴とする集積回路デバイス。 - 前記バイアが、第1の層の前記コンタクトに対して代わりのコンタクトを提供し、前記コンタクトが1〜64の範囲で変化することを特徴とする請求項1に記載の集積回路デバイス。
- 前記相互接続層の選択された部分の前記導電性部材が、接地電位に接続されており、
前記接地電位に対する前記複数の結合パッドの数が2〜512の範囲にあることを特徴とする請求項1に記載の集積回路デバイス。 - 前記相互接続層の選択された部分の前記導電性部材が、所定の電位に接続されており、
前記所定の電位に対する前記複数の結合パッドの数が2〜512の範囲にあることを特徴とする請求項1に記載の集積回路デバイス。 - 前記基板がダイヤモンド、ストレインドシリコン、シリコンカーバイドのうちの1つを備えることを特徴とする請求項1に記載の集積回路デバイス。
- 基板を提供するステップと、
前記基板上に配置された、パターン化された特徴部を各々が備え、該パターン化された特徴が少なくとも一つの電気コンタクトを備える複数のマイクロ電子デバイスを形成するステップと、
前記複数のマイクロ電子デバイスに電力を分配するための複数の相互接続層であって、該相互接続層が、各々複数の導電性部材を備え、少なくとも一つの連続する相互接続層が、少なくとも一つの他の相互接続層の前記導電性部材に跨っている相互接続層を形成するステップと、
前記相互接続層の複数の前記導電性部材の少なくとも一つに接続する複数の結合パッドを提供するステップと、を備え、
少なくとも一つのマイクロ電子デバイスと電気的に接続する導電性相互接続を備える第1の層を提供するステップと、
前記第1の層のラインに対して直角に整列された導電性のラインを備える第2の層であって、前記第2の層のラインが前記第1の層のラインと電気的に接触されている第2の層を提供するステップと、
前記第2の層のラインに対して直角に整列された導電性のラインを備える第3の層であって、前記第3の層のラインが前記第2の層のラインと電気的に接触されている第3の層を提供するステップと、
前記第1の層を前記第2の層に相互接続し、且つ前記第3の層を前記第2の層に相互接続するための複数のバイアを提供するステップと、を備えた集積回路デバイスの製造方法。 - 前記第1の相互接続層の前記導電体が、各マイクロ電子デバイスの少なくとも一つのコンタクトと接触することを特徴とする請求項6に記載の集積回路デバイスの製造方法。
- 前記基板がダイヤモンド、ストレインドシリコンのいずれかを備えることを特徴とする請求項6に記載の集積回路デバイスの製造方法。
- 基板と、
複数のマイクロ電子デバイス層であって、前記層が各々複数のマイクロ電子デバイスを備え、複数の相互接続層が前記複数のマイクロ電子デバイスに電力を分配するマイクロ電子デバイスと、
前記デバイス層を電気的に接続するための複数の導電性相互接続部を備える変位相互接続層と、
複数の部材のうちの少なくとも一つと接続された複数の結合パッドと、を備えた三次元集積回路デバイス。 - 前記マイクロ電子デバイスが、デバイス層内に配置されたパターン化された特徴部を含み、前記パターン化された特徴部が、少なくとも一つの電気コンタクトを備えることを特徴とする請求項9に記載の三次元集積回路デバイス。
- 前記相互接続層が各々が複数の導電性部材を備え、少なくとも一つの連続する前記相互接続層が、少なくとも一つの他の相互接続層の前記導電性部材に跨っていることを特徴とする請求項9に記載の三次元集積回路デバイス。
- 前記変位層が更に、
少なくとも一つのデバイス層上に実質的に形成された誘電体層と、
シリコンを備えた第1の半導体層と、
前記第1の半導体層の全体にわたる金属を備える導電体シード層と、
シリコンを備えた第2の半導体層と、を備えることを特徴とする請求項9に記載の三次元集積回路デバイス。
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DE102004055929B4 (de) * | 2004-11-19 | 2014-05-22 | Qimonda Ag | Nichtflüchtige Speicherzellen-Anordnung |
TWI251301B (en) * | 2004-11-29 | 2006-03-11 | Unimicron Technology Corp | Substrate core and method for fabricating the same |
CN1893084A (zh) * | 2005-07-07 | 2007-01-10 | 松下电器产业株式会社 | 半导体装置 |
KR100667653B1 (ko) * | 2005-07-11 | 2007-01-12 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
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US7824990B2 (en) * | 2005-12-05 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-metal-oxide high-K gate dielectrics |
US20070194450A1 (en) * | 2006-02-21 | 2007-08-23 | Tyberg Christy S | BEOL compatible FET structure |
JP2007294499A (ja) * | 2006-04-21 | 2007-11-08 | Nec Electronics Corp | 半導体装置 |
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JP5298470B2 (ja) * | 2007-07-11 | 2013-09-25 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
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US7233032B2 (en) | 2007-06-19 |
US20050124095A1 (en) | 2005-06-09 |
CN2781572Y (zh) | 2006-05-17 |
TWI250612B (en) | 2006-03-01 |
US20050121793A1 (en) | 2005-06-09 |
JP2005175415A (ja) | 2005-06-30 |
US7202566B2 (en) | 2007-04-10 |
TW200529364A (en) | 2005-09-01 |
CN1641871A (zh) | 2005-07-20 |
JP4836055B2 (ja) | 2011-12-14 |
SG112935A1 (en) | 2005-07-28 |
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