JP2008103658A - 薄膜トランジスタ基板の製造方法 - Google Patents

薄膜トランジスタ基板の製造方法 Download PDF

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Publication number
JP2008103658A
JP2008103658A JP2007044999A JP2007044999A JP2008103658A JP 2008103658 A JP2008103658 A JP 2008103658A JP 2007044999 A JP2007044999 A JP 2007044999A JP 2007044999 A JP2007044999 A JP 2007044999A JP 2008103658 A JP2008103658 A JP 2008103658A
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JP
Japan
Prior art keywords
reaction
pattern
etching
conductive film
active layer
Prior art date
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Withdrawn
Application number
JP2007044999A
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English (en)
Japanese (ja)
Other versions
JP2008103658A5 (enExample
Inventor
Seung-Ha Choi
昇 夏 崔
Shoko Kin
湘 甲 金
▼文▲ 錫 ▼呉▲
Min-Seok Oh
Shin-Il Choi
新 逸 崔
Dae-Ok Kim
大 玉 金
Hong-Kee Chin
洪 基 秦
Young-Ho Jeong
榮 鎬 丁
Yu-Gwang Jeong
有 光 丁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2008103658A publication Critical patent/JP2008103658A/ja
Publication of JP2008103658A5 publication Critical patent/JP2008103658A5/ja
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0231Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2007044999A 2006-10-18 2007-02-26 薄膜トランジスタ基板の製造方法 Withdrawn JP2008103658A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060101428A KR20080035150A (ko) 2006-10-18 2006-10-18 박막 트랜지스터 기판의 제조 방법

Publications (2)

Publication Number Publication Date
JP2008103658A true JP2008103658A (ja) 2008-05-01
JP2008103658A5 JP2008103658A5 (enExample) 2010-04-08

Family

ID=38941885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007044999A Withdrawn JP2008103658A (ja) 2006-10-18 2007-02-26 薄膜トランジスタ基板の製造方法

Country Status (6)

Country Link
US (1) US20080093334A1 (enExample)
EP (1) EP1914802A2 (enExample)
JP (1) JP2008103658A (enExample)
KR (1) KR20080035150A (enExample)
CN (1) CN101165882A (enExample)
TW (1) TW200820446A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026975A1 (ja) 2008-09-02 2010-03-11 独立行政法人産業技術総合研究所 非晶質アルミニウムケイ酸塩の製造方法、及びその方法により得られた非晶質アルミニウムケイ酸塩、並びにそれを用いた吸着剤

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101682078B1 (ko) 2010-07-30 2016-12-05 삼성디스플레이 주식회사 박막 트랜지스터 표시판의 제조 방법
JP5836846B2 (ja) * 2011-03-11 2015-12-24 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
KR102030797B1 (ko) * 2012-03-30 2019-11-11 삼성디스플레이 주식회사 박막 트랜지스터 표시판 제조 방법
CN107895713B (zh) * 2017-11-30 2020-05-05 深圳市华星光电半导体显示技术有限公司 Tft基板制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3191745B2 (ja) * 1997-04-23 2001-07-23 日本電気株式会社 薄膜トランジスタ素子及びその製造方法
US7479205B2 (en) * 2000-09-22 2009-01-20 Dainippon Screen Mfg. Co., Ltd. Substrate processing apparatus
US8148895B2 (en) * 2004-10-01 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method of the same
KR100614323B1 (ko) * 2004-12-30 2006-08-21 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026975A1 (ja) 2008-09-02 2010-03-11 独立行政法人産業技術総合研究所 非晶質アルミニウムケイ酸塩の製造方法、及びその方法により得られた非晶質アルミニウムケイ酸塩、並びにそれを用いた吸着剤

Also Published As

Publication number Publication date
CN101165882A (zh) 2008-04-23
US20080093334A1 (en) 2008-04-24
TW200820446A (en) 2008-05-01
KR20080035150A (ko) 2008-04-23
EP1914802A2 (en) 2008-04-23

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