JP2008004237A - 半導体メモリテスタ - Google Patents
半導体メモリテスタ Download PDFInfo
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- JP2008004237A JP2008004237A JP2006175545A JP2006175545A JP2008004237A JP 2008004237 A JP2008004237 A JP 2008004237A JP 2006175545 A JP2006175545 A JP 2006175545A JP 2006175545 A JP2006175545 A JP 2006175545A JP 2008004237 A JP2008004237 A JP 2008004237A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000012360 testing method Methods 0.000 claims abstract description 26
- 238000005070 sampling Methods 0.000 claims description 6
- 230000002950 deficient Effects 0.000 abstract description 2
- 240000007320 Pinus strobus Species 0.000 description 17
- 238000010586 diagram Methods 0.000 description 11
- 238000005259 measurement Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56012—Timing aspects, clock generation, synchronisation
Abstract
【解決手段】テスト対象メモリデバイスの良否判定を行う半導体メモリテスタであって、前記テスト対象メモリデバイスが出力するクロックに基づくタイミングで前記テスト対象メモリデバイスの出力と期待値とを比較する測定部を有することを特徴とするもの。
【選択図】図1
Description
図1は本発明の実施形態の一例を示すブロック図である。テスタ100はDUT200に対して各種の試験信号を与え、DUT200はテスタ100から入力される試験信号に基づく応答信号をテスタ100に対して出力する。そして、テスタ100は、DUT200から入力される応答信号があらかじめ設定されている所定の時間関係を満たしているか否かを判断して良否判定を行う。
信号発生部Aには、DUT200に与えるフレームパターンを出力フレームパターンとしてフォーマッタ123〜12nに入力するとともにDUT200から出力されるフレームの良否判断の基準になる期待値フレームパターンを入力フレームパターンとして信号測定部Bのフェイル判定部に入力するフレームパターン発生部101、タイミング発生部111とフォーマッタ121とドライバ131とで構成される基準クロックの出力系統、タイミング発生部112とフォーマッタ122とドライバ132とで構成されるDQS入力ピンの出力系統、タイミング発生部113〜11nとフォーマッタ123〜12nとドライバ133〜13nとで構成される所定のパケットフレームを出力するための複数のコマンド/アドレス/データピンの出力系統が設けられている。
内部クロック発生回路201は、テスタ100から入力される基準クロック(例えば133MHz)を逓倍(例えば24倍)して所定周波数(例えば3200MHz)の内部クロックDQSを生成し、入力クロック同期回路202の一方の入力端子および出力クロック回路203に出力する。
200 DUT
111〜11n タイミング発生部
121〜12n フォーマッタ
131〜13n ドライバ
141 レシーバ
142〜14n コンパレータ
151 分周分配ユニット
152〜15n 分配ユニット
161〜16n フェイル判定部
171〜17n タイミング発生部
Claims (5)
- テスト対象メモリデバイスの良否判定を行う半導体メモリテスタであって、
前記テスト対象メモリデバイスが出力するクロックに基づくタイミングで前記テスト対象メモリデバイスの出力と期待値とを比較する測定部を有することを特徴とする半導体メモリテスタ。 - 前記測定部は、
前記テスト対象メモリデバイスの出力データが入力されるコンパレータと、
このコンパレータの出力を比較タイミングでサンプリングするサンプリング部と、
このサンプリング部の出力と期待値を比較してテスト対象メモリデバイスの良否判定を行うフェイル判定部、を有することを特徴とする請求項1に記載の半導体メモリテスタ。 - 前記測定部は、
前記テスト対象メモリデバイスの出力データの遅延時間を設定する可変遅延素子を有することを特徴とする請求項1または請求項2に記載の半導体メモリテスタ。 - 前記測定部は、
テスト対象メモリデバイスが出力するクロックを分周して比較タイミングを生成する分周手段を有することを特徴とする請求項1から請求項3のいずれかに記載の半導体メモリテスタ。 - 前記テスト対象メモリデバイスは、内部でクロックを生成することを特徴とする請求項1から請求項4のいずれかに記載の半導体メモリテスタ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006175545A JP4957092B2 (ja) | 2006-06-26 | 2006-06-26 | 半導体メモリテスタ |
KR1020070059499A KR100903753B1 (ko) | 2006-06-26 | 2007-06-18 | 반도체 메모리 테스터 |
US11/819,025 US7644324B2 (en) | 2006-06-26 | 2007-06-25 | Semiconductor memory tester |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006175545A JP4957092B2 (ja) | 2006-06-26 | 2006-06-26 | 半導体メモリテスタ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008004237A true JP2008004237A (ja) | 2008-01-10 |
JP4957092B2 JP4957092B2 (ja) | 2012-06-20 |
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JP2006175545A Active JP4957092B2 (ja) | 2006-06-26 | 2006-06-26 | 半導体メモリテスタ |
Country Status (3)
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US (1) | US7644324B2 (ja) |
JP (1) | JP4957092B2 (ja) |
KR (1) | KR100903753B1 (ja) |
Cited By (3)
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---|---|---|---|---|
JP2012247316A (ja) * | 2011-05-27 | 2012-12-13 | Advantest Corp | 試験装置および試験方法 |
US8718123B2 (en) | 2011-05-27 | 2014-05-06 | Advantest Corporation | Test apparatus and test method |
US8898531B2 (en) | 2011-05-27 | 2014-11-25 | Advantest Corporation | Test apparatus and test method |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090119542A1 (en) * | 2007-11-05 | 2009-05-07 | Advantest Corporation | System, method, and program product for simulating test equipment |
JP2010169480A (ja) * | 2009-01-21 | 2010-08-05 | Elpida Memory Inc | 半導体デバイス試験装置及び半導体装置 |
WO2011127973A1 (en) * | 2010-04-14 | 2011-10-20 | Verigy (Singapore) Pte. Ltd. | Apparatus and method for testing a plurality of devices under test |
JP2012247317A (ja) | 2011-05-27 | 2012-12-13 | Advantest Corp | 試験装置および試験方法 |
KR101337333B1 (ko) * | 2012-02-29 | 2013-12-06 | 주식회사 유니테스트 | 반도체소자 테스터용 신호발생장치의 포맷터 |
US9217772B2 (en) * | 2012-07-31 | 2015-12-22 | Infineon Technologies Ag | Systems and methods for characterizing devices |
TWI562157B (en) * | 2015-05-07 | 2016-12-11 | Winbond Electronics Corp | Memory unit and testing method thereof |
CN106297897B (zh) * | 2015-05-27 | 2019-07-30 | 华邦电子股份有限公司 | 存储单元及其测试方法 |
CN106328211B (zh) * | 2015-06-15 | 2021-06-08 | 中兴通讯股份有限公司 | 一种实现时序测试的方法及装置 |
US11848070B2 (en) * | 2021-11-10 | 2023-12-19 | Micron Technology, Inc. | Memory with DQS pulse control circuitry, and associated systems, devices, and methods |
Citations (1)
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JP2002042498A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 半導体記憶装置、補助装置および試験装置 |
Family Cites Families (17)
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JP4282170B2 (ja) * | 1999-07-29 | 2009-06-17 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4612150B2 (ja) * | 2000-05-24 | 2011-01-12 | 株式会社アドバンテスト | 半導体デバイス試験装置 |
JP4782271B2 (ja) * | 2000-07-06 | 2011-09-28 | 株式会社アドバンテスト | 半導体デバイス試験方法・半導体デバイス試験装置 |
DE10034852A1 (de) * | 2000-07-18 | 2002-02-07 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen |
DE10034899C1 (de) * | 2000-07-18 | 2002-07-04 | Infineon Technologies Ag | System zum Test schneller synchroner Halbleiterschaltungen |
DE10034855B4 (de) * | 2000-07-18 | 2006-05-11 | Infineon Technologies Ag | System zum Test von schnellen integrierten Digitalschaltungen und BOST-Halbleiterschaltungsbaustein als Testschaltkreis |
GB0026849D0 (en) * | 2000-11-03 | 2000-12-20 | Acuid Corp Ltd | DDR SDRAM memory test system with fault strobe synchronization |
JP4125492B2 (ja) | 2001-02-01 | 2008-07-30 | 株式会社日立製作所 | 半導体集積回路装置とテスト方法及び半導体集積回路装置の製造方法 |
DE10115880B4 (de) * | 2001-03-30 | 2007-01-25 | Infineon Technologies Ag | Testschaltung zum kritischen Testen einer synchronen Speicherschaltung |
US6754868B2 (en) * | 2001-06-29 | 2004-06-22 | Nextest Systems Corporation | Semiconductor test system having double data rate pin scrambling |
US7003697B2 (en) * | 2001-07-02 | 2006-02-21 | Nextest Systems, Corporation | Apparatus having pattern scrambler for testing a semiconductor device and method for operating same |
KR100988486B1 (ko) * | 2002-03-08 | 2010-10-20 | 주식회사 아도반테스토 | 반도체 시험 장치 및 그 타이밍 측정 방법 |
JP2003307545A (ja) * | 2002-04-15 | 2003-10-31 | Hitachi Ltd | 半導体検査装置、半導体集積回路装置、検査方法および製造方法 |
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US7036053B2 (en) * | 2002-12-19 | 2006-04-25 | Intel Corporation | Two dimensional data eye centering for source synchronous data transfers |
KR101080551B1 (ko) * | 2003-07-31 | 2011-11-04 | 주식회사 아도반테스토 | 시험 장치 |
KR100639678B1 (ko) | 2004-11-16 | 2006-10-30 | 삼성전자주식회사 | 테스트 장치 |
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- 2006-06-26 JP JP2006175545A patent/JP4957092B2/ja active Active
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- 2007-06-18 KR KR1020070059499A patent/KR100903753B1/ko active IP Right Grant
- 2007-06-25 US US11/819,025 patent/US7644324B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002042498A (ja) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | 半導体記憶装置、補助装置および試験装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012247316A (ja) * | 2011-05-27 | 2012-12-13 | Advantest Corp | 試験装置および試験方法 |
US8718123B2 (en) | 2011-05-27 | 2014-05-06 | Advantest Corporation | Test apparatus and test method |
US8898531B2 (en) | 2011-05-27 | 2014-11-25 | Advantest Corporation | Test apparatus and test method |
Also Published As
Publication number | Publication date |
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US7644324B2 (en) | 2010-01-05 |
KR20070122373A (ko) | 2007-12-31 |
JP4957092B2 (ja) | 2012-06-20 |
KR100903753B1 (ko) | 2009-06-18 |
US20070297255A1 (en) | 2007-12-27 |
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