JP2007538468A5 - - Google Patents

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Publication number
JP2007538468A5
JP2007538468A5 JP2007527274A JP2007527274A JP2007538468A5 JP 2007538468 A5 JP2007538468 A5 JP 2007538468A5 JP 2007527274 A JP2007527274 A JP 2007527274A JP 2007527274 A JP2007527274 A JP 2007527274A JP 2007538468 A5 JP2007538468 A5 JP 2007538468A5
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Japan
Prior art keywords
delay
feedback clock
clock
logic value
delayed
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JP2007527274A
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English (en)
Japanese (ja)
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JP4678541B2 (ja
JP2007538468A (ja
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Priority claimed from US10/848,261 external-priority patent/US7421606B2/en
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Publication of JP2007538468A5 publication Critical patent/JP2007538468A5/ja
Application granted granted Critical
Publication of JP4678541B2 publication Critical patent/JP4678541B2/ja
Anticipated expiration legal-status Critical
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JP2007527274A 2004-05-18 2005-05-04 進歩した位相等化を用いたｄｌｌ位相検出 Expired - Lifetime JP4678541B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/848,261 US7421606B2 (en) 2004-05-18 2004-05-18 DLL phase detection using advanced phase equalization
US10/848,261 2004-05-18
PCT/US2005/015717 WO2005117265A1 (en) 2004-05-18 2005-05-04 Dll phase detection using advanced phase equalisation

Publications (3)

Publication Number Publication Date
JP2007538468A JP2007538468A (ja) 2007-12-27
JP2007538468A5 true JP2007538468A5 (enExample) 2010-08-05
JP4678541B2 JP4678541B2 (ja) 2011-04-27

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ID=34968497

Family Applications (1)

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JP2007527274A Expired - Lifetime JP4678541B2 (ja) 2004-05-18 2005-05-04 進歩した位相等化を用いたｄｌｌ位相検出

Country Status (7)

Country Link
US (3) US7421606B2 (enExample)
EP (1) EP1751868B1 (enExample)
JP (1) JP4678541B2 (enExample)
KR (1) KR101144519B1 (enExample)
DE (1) DE602005013772D1 (enExample)
TW (1) TWI345882B (enExample)
WO (1) WO2005117265A1 (enExample)

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