JP2007533137A - ＳＯＩ（ｓｅｍｉｃｏｎｄｕｃｔｏｒｏｎｉｎｓｕｌａｔｏｒ）基板、およびこの基板から形成されるデバイス - Google Patents

ＳＯＩ（ｓｅｍｉｃｏｎｄｕｃｔｏｒｏｎｉｎｓｕｌａｔｏｒ）基板、およびこの基板から形成されるデバイス Download PDF

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JP2007533137A
JP2007533137A JP2007507361A JP2007507361A JP2007533137A JP 2007533137 A JP2007533137 A JP 2007533137A JP 2007507361 A JP2007507361 A JP 2007507361A JP 2007507361 A JP2007507361 A JP 2007507361A JP 2007533137 A JP2007533137 A JP 2007533137A
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layer
lattice
silicon
semiconductor
semiconductor material
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Japanese (ja)
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JP2007533137A5 (https=
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シャン キ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2007533137A publication Critical patent/JP2007533137A/ja
Publication of JP2007533137A5 publication Critical patent/JP2007533137A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Inorganic Insulating Materials (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2007507361A 2004-04-07 2005-03-28 ＳＯＩ（ｓｅｍｉｃｏｎｄｕｃｔｏｒｏｎｉｎｓｕｌａｔｏｒ）基板、およびこの基板から形成されるデバイス Pending JP2007533137A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/819,441 US7005302B2 (en) 2004-04-07 2004-04-07 Semiconductor on insulator substrate and devices formed therefrom
PCT/US2005/010574 WO2005101521A1 (en) 2004-04-07 2005-03-28 Semiconductor on insulator substrate and devices formed therefrom

Publications (2)

Publication Number Publication Date
JP2007533137A true JP2007533137A (ja) 2007-11-15
JP2007533137A5 JP2007533137A5 (https=) 2008-05-15

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ID=34964796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007507361A Pending JP2007533137A (ja) 2004-04-07 2005-03-28 ＳＯＩ（ｓｅｍｉｃｏｎｄｕｃｔｏｒｏｎｉｎｓｕｌａｔｏｒ）基板、およびこの基板から形成されるデバイス

Country Status (8)

Country Link
US (2) US7005302B2 (https=)
JP (1) JP2007533137A (https=)
KR (1) KR101093785B1 (https=)
CN (1) CN1998088B (https=)
DE (1) DE112005000775B4 (https=)
GB (1) GB2429114B (https=)
TW (1) TWI360833B (https=)
WO (1) WO2005101521A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186493A (ja) * 2012-05-14 2012-09-27 Sony Corp 半導体装置
JP2013102203A (ja) * 2007-02-21 2013-05-23 Internatl Business Mach Corp <Ibm> 横方向に可変の仕事関数を有するゲート電極を含む半導体構造体

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7365357B2 (en) * 2005-07-22 2008-04-29 Translucent Inc. Strain inducing multi-layer cap
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7495290B2 (en) * 2005-12-14 2009-02-24 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
KR100649874B1 (ko) * 2005-12-29 2006-11-27 동부일렉트로닉스 주식회사 에스오아이 웨이퍼를 이용한 트랜지스터 제조 방법
DE102006035669B4 (de) * 2006-07-31 2014-07-10 Globalfoundries Inc. Transistor mit einem verformten Kanalgebiet, das eine leistungssteigernde Materialzusammensetzung aufweist und Verfahren zur Herstellung
KR100850899B1 (ko) * 2007-02-09 2008-08-07 엘지전자 주식회사 박막 트랜지스터 및 그 제조방법
KR100994995B1 (ko) * 2007-08-07 2010-11-18 삼성전자주식회사 ＤｙＳｃ０３ 막을 포함하는 반도체 박막의 적층 구조 및 그 형성방법
US7692224B2 (en) * 2007-09-28 2010-04-06 Freescale Semiconductor, Inc. MOSFET structure and method of manufacture
JP5190275B2 (ja) * 2008-01-09 2013-04-24 パナソニック株式会社 半導体メモリセル及びそれを用いた半導体メモリアレイ
KR101535222B1 (ko) * 2008-04-17 2015-07-08 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US8835955B2 (en) * 2010-11-01 2014-09-16 Translucent, Inc. IIIOxNy on single crystal SOI substrate and III n growth platform
CN102751231A (zh) * 2012-03-13 2012-10-24 清华大学 一种半导体结构及其形成方法
CN102683345B (zh) * 2012-05-22 2015-04-15 清华大学 半导体结构及其形成方法
CN102683388B (zh) * 2012-05-30 2016-06-29 清华大学 半导体结构及其形成方法
CN102916039B (zh) * 2012-10-19 2016-01-20 清华大学 具有氧化铍的半导体结构
CN102903739B (zh) * 2012-10-19 2016-01-20 清华大学 具有稀土氧化物的半导体结构
US9570588B2 (en) * 2014-12-29 2017-02-14 Globalfoundries Inc. Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
CN108060457A (zh) * 2017-12-21 2018-05-22 苏州晶享嘉世光电科技有限公司 一种钪酸钆钇晶体及熔体法晶体生长方法
CN110284192A (zh) * 2019-06-17 2019-09-27 南京同溧晶体材料研究院有限公司 一种掺铒钪酸钆3μm中红外波段激光晶体及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219524A (ja) * 1996-02-09 1997-08-19 Toshiba Corp 半導体装置及びその製造方法
JP2001110801A (ja) * 1999-10-05 2001-04-20 Takeshi Yao パターン形成方法、並びに電子素子、光学素子及び回路基板
JP2003303971A (ja) * 2002-04-09 2003-10-24 Matsushita Electric Ind Co Ltd 半導体基板及び半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5830270A (en) * 1996-08-05 1998-11-03 Lockheed Martin Energy Systems, Inc. CaTiO3 Interfacial template structure on semiconductor-based material and the growth of electroceramic thin-films in the perovskite class
US6603156B2 (en) 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US20020195599A1 (en) 2001-06-20 2002-12-26 Motorola, Inc. Low-defect semiconductor structure, device including the structure and method for fabricating structure and device
US6933566B2 (en) 2001-07-05 2005-08-23 International Business Machines Corporation Method of forming lattice-matched structure on silicon and structure formed thereby
US20030020070A1 (en) * 2001-07-25 2003-01-30 Motorola, Inc. Semiconductor structure for isolating high frequency circuitry and method for fabricating
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
JP4090716B2 (ja) 2001-09-10 2008-05-28 雅司 川崎 薄膜トランジスタおよびマトリクス表示装置
JP4034627B2 (ja) * 2001-09-28 2008-01-16 テキサス インスツルメンツ インコーポレイテツド 集積回路及びその製造方法
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6730576B1 (en) 2002-12-31 2004-05-04 Advanced Micro Devices, Inc. Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219524A (ja) * 1996-02-09 1997-08-19 Toshiba Corp 半導体装置及びその製造方法
JP2001110801A (ja) * 1999-10-05 2001-04-20 Takeshi Yao パターン形成方法、並びに電子素子、光学素子及び回路基板
JP2003303971A (ja) * 2002-04-09 2003-10-24 Matsushita Electric Ind Co Ltd 半導体基板及び半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013102203A (ja) * 2007-02-21 2013-05-23 Internatl Business Mach Corp <Ibm> 横方向に可変の仕事関数を有するゲート電極を含む半導体構造体
JP2012186493A (ja) * 2012-05-14 2012-09-27 Sony Corp 半導体装置

Also Published As

Publication number Publication date
CN1998088A (zh) 2007-07-11
DE112005000775B4 (de) 2012-10-31
GB2429114B (en) 2009-04-01
GB2429114A (en) 2007-02-14
US20050224879A1 (en) 2005-10-13
US7005302B2 (en) 2006-02-28
US20060138542A1 (en) 2006-06-29
DE112005000775T5 (de) 2007-05-31
GB0619840D0 (en) 2006-11-29
US7221025B2 (en) 2007-05-22
KR20070012458A (ko) 2007-01-25
TWI360833B (en) 2012-03-21
WO2005101521A1 (en) 2005-10-27
KR101093785B1 (ko) 2011-12-19
TW200539278A (en) 2005-12-01
CN1998088B (zh) 2010-08-25

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