Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Definitions

• MOSFETs insulated gate field effect transistors
• ICs integrated circuits
• Figure 1 shows a cross sectional view of a conventional MOSFET device.
• the MOSFET is fabricated on a bulk silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10.
• the MOSFET is comprised of a gate 14 and a channel region 16 that are separated by a thin gate insulator 18 such as silicon oxide or silicon oxynitride.
• Source and drain suicides 28 are formed on the deep source and drain regions 20 to provide ohmic contacts and reduce contact resistance.
• the suicides 28 are comprised of the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni).
• a suicide 30 is also formed at the upper surface of the gate 14.
• SOI semiconductor on insulator
• MOSFETs are formed on a substrate that includes a layer of a dielectric material beneath the MOSFET active regions. SOI devices have a number of advantages over devices formed in a bulk semiconductor substrate, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
• FIG. 2 shows an example of a conventional fully depleted SOI MOSFET.
• the SOI MOSFET is formed on an SOI substrate comprised of a silicon layer 32 and a dielectric layer 34.
• the MOSFET structure is formed on an isolated region 36 of a silicon layer that has been etched to define individual islands on which individual devices are formed.
• a thin undoped channel region 16 is located at the center of the silicon region 36.
• Source and drain extensions 24 are implanted into the silicon region 36 at opposing sides of a gate 14 formed on a gate insulator 18.
• elevated source and drain regions 38 are grown on the silicon region 38, and suicide source and drain contacts 28 and a suicide gate contact 30 are then formed.
• a moderate tensile strain increases electron mobility, and a more substantial tensile strain increases hole mobility.
• the amount of tensile strain increases with the proportion of germanium in the silicon germanium lattice. It has also been found that a moderate compressive strain improves hole mobility.
• An example of a MOSFET incorporating a tensile strained silicon layer is shown in Figure 3.
• MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10.
• the silicon germanium layer is typically a graded layer in which the germanium content is gradually increased from zero to between 10% to 40%, depending on the amount of strain that is desired.
• An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32.
• the MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 24, a gate oxide layer 18, a gate 14 surrounded by a protective layer 26, a spacer 22, source and drain suicides 28, a gate suicide 30, and shallow trench isolations 12.
• the strained silicon material in the channel region 16 provides enhanced carrier mobility between the source and drain.
• Strained silicon may also be incorporated into a MOSFET formed on an SOI substrate.
• Figure 4 shows an example of a strained silicon SOI MOSFET.
• the MOSFET is formed on an SOI substrate that comprises a silicon germanium layer that overlies a dielectric layer 40.
• the silicon germanium layer is patterned to define isolated regions 42 on which individual MOSFETs are formed.
• a strained silicon layer 44 is grown on the silicon germanium region 42.
• the MOSFET is then formed in a manner similar to that of the conventional strained silicon device of Figure 3. It is difficult to form a fully depleted SOI device that incorporates a strained silicon channel.
• a fully depleted SOI MOSFET preferably has a channel region thickness that is no more than approximately one third of the channel length.
• CMP chemical mechanical polishing
• deposited silicon takes the form of polycrystalline silicon or amorphous silicon, which is composed of individual grains each having a crystal lattice that is randomly oriented with respect to those of the surrounding grains.
• These forms of silicon exhibit poor conductivity compared to single crystal silicon and therefore are not desirable for use in the active regions of MOSFETs. Therefore, to date it has generally not been possible to grow single crystal silicon on other materials, particularly conventional dielectrics such as silicon oxide and silicon oxynitride, whose structures are essentially amorphous or do not match the silicon lattice. Therefore the conventional techniques for producing semiconductor on insulator devices are not satisfactory for producing devices having small critical dimensions and devices incorporating strained silicon.
• Embodiments of the invention provide semiconductor on insulator devices comprised of a dielectric layer upon which a semiconductor layer may be directly grown.
• the properties of the dielectric layer and the properties of the semiconductor layer may be chosen so that the dielectric layer imparts a tensile strain or a compressive strain to the semiconductor material.
• Further embodiments of the invention provide methods for formation of such devices.
• Certain preferred embodiments of the invention utilize a layer of a dielectric material having a perovskite lattice structure. The perovskite lattice has been found to provide a suitable template for growth of diamond lattice semiconductors.
• dielectrics having a perovskite lattice structure include rare earth scandate compounds such as gadolinium scandate (GdSc0 3 ), dysprosium scandate (DySc0 3 ), and alloys of gadolinium and dysprosium scandate (Gd ⁇ _ ⁇ Dy x Sc0 3 ).
• semiconductor materials having a diamond lattice structure that is compatible with the rare earth scandates include silicon, germanium, alloys of silicon and germanium, and III-V type semiconductor materials such as gallium arsenide.
• the stoichiometric compositions of the rare earth scandate and the semiconductor material may be designed such that the rare earth scandate imparts a tensile strain or a compressive strain to the semiconductor material grown thereon.
• Such dielectric materials may be used as a dielectric layer in semiconductor on insulator MOSFETs, allowing a thin semiconductor layer to be grown directly on the dielectric jiayer.
• Figure 1 shows a conventional MOSFET formed in accordance with conventional processing
• Figure 2 shows a conventional SOI MOSFET
• Figure 3 shows a conventional strained silicon MOSFET
• Figure 4 shows a strained silicon MOSFET formed on an SOI substrate using conventional techniques
• Figures 5a, 5b and 5c show the perovskite and diamond lattices, and the manner in which these lattices are compatible
• Figures 6a, 6b, 6c, 6d, 6e and 6f show structures formed during production of a strained silicon SOI MOSFET in accordance with an exemplary embodiment of the invention
• Figure 7 shows elements of a CMOS device in accordance with an exemplary embodiment.
• Examples of dielectrics having a perovskite lattice structure include rare earth scandate compounds such as gadolinium scandate (GdSc0 3 ), dysprosium scandate (DySc0 3 ), and alloys of gadolinium and dysprosium scandate (Gd ⁇ _ x Dy x Sc0 3 ).
• the stoichiometric compositions of the rare earth scandate and the semiconductor material may be designed to provide a lattice mismatch such that the rare earth scandate imparts a tensile strain or a compressive strain to the semiconductor material grown thereon.
• a layer of the rare earth scandate gadolinium scandate (GdSc0 3 ) is used as a dielectric layer and as a supporting layer for growth of a tensile strained silicon or silicon germanium layer.
• Single crystal gadolinium scandate has a dielectric constant of 22-35 and is therefore an excellent dielectric material for SOI applications.
• Figure 5a illustrates the (001) faces of unit cells in the perovskite lattice of gadolinium scandate (GdSc0 3 ). In its ideal form, the perovskite lattice has Pm3m symmetry. In other words, the unit cell of the lattice is a cube with one of the cations (e.g.
• the diamond lattice is essentially comprised of two interpenetrating face-centered cubic lattices, each offset from the other by V of the length of the lattice constant along each of the three spatial axes.
• the diamond lattice is structurally different than the perovskite lattice, the two lattices may be compatible for purposes of epitaxial growth depending on the spacing of the atoms in each lattice.
• the atoms at the face of the silicon diamond lattice align with the empty faces of the gadolinium scandate perovskite lattice when the (001) plane of the silicon lattice is rotated by 45 degrees with respect to the (001) plane of the gadolinium scandate lattice.
• the gadolinium scandate lattice is capable of serving as a template for growth of silicon.
• the lattice constant at the (001) faces of the gadolinium scandate lattice is 3.94 A
• the lattice constant at the (001) faces of the relaxed silicon lattice is 5.431 A.
• the diagonal distance between the centers of the faces in the gadolinium scandate lattice is 5.572 A, which is approximately 2.7% greater than the 5.431 A lattice constant of pure relaxed silicon.
• pure relaxed germanium has a lattice constant of germanium 5.657 A, which is approximately 4.2% greater than that of silicon.
• Conventional strained silicon devices use a supporting layer of silicon germanium Si ⁇ . ⁇ Ge x having a lattice constant that is between those two values and depends on the amount of germanium in the lattice. Germanium percentages between approximately 10% and 40% are typically used in conventional strained silicon devices, resulting in lattices having lattice constants that are effectively between .9% to 1. ⁇ o greater than that of silicon.
• the effective lattice constant may be defined as the distance between the centers of diagonally oriented unit cell faces.
• the diagonal distances between face centers will depend on the direction of measurement. In such cases, the effective lattice constant may be defined as the average of the two diagonal distances between face centers.
• the effective lattice constant may be defined as the distance between diagonal face centers in the direction of either the greater or lesser distance.
• the exemplary measurements given above are specific to GdSc0 3 , and other rare earth scandates with different effective lattice constants may be designed to produce a desired degree of mismatch with respect to an epitaxial semiconductor lattice.
• the compound dysprosium scandate (DySc0 3 ) may be employed.
• DySc0 3 has an effective lattice constant of approximately 5.6 A.
• a rare earth scandate alloy such as Gd ! _ ⁇ Dy x Sc0 3 may be designed with stoichiometric proportions of gadolinium and dysprosium that are selected to provide a desired effective lattice constant.
• the effective lattice constant of the rare earth scandate is preferably greater than the lattice constant of relaxed silicon (5.431 A), and preferably less than the lattice constant of relaxed germanium (5.657 A), and is more preferably less than the lattice constant of a relaxed silicon germanium alloy comprised of 40% germanium (5.519 A).
• a dielectric layer having a perovskite lattice structure such as a rare earth scandate
• a dielectric layer having a perovskite lattice structure such as a rare earth scandate
• the ratios of silicon and germanium in the silicon germanium alloy may be chosen with respect to the effective lattice constant of the dielectric substrate to produce a variety of effects.
• the silicon germanium alloy may be designed to have a lattice constant that is smaller than the effective lattice constant of the dielectric material, resulting in the application of a desired amount of tensile strain in the silicon germanium alloy.
• the silicon germanium alloy may be designed to have a lattice constant that is greater than the effective lattice constant of the dielectric material, resulting in the application of a desired amount of compressive strain on the silicon germanium alloy.
• Compressively strained germanium may also be grown on the rare earth scandate dielectric. Further, given a substrate having a layer of a rare earth scandate with a given effective lattice constant, silicon and silicon germanium alloys having different stoichiometric ratios may be grown at selected locations on the substrate to provide coexisting regions of tensile and compressively strained semiconductor materials.
• CMOS devices comprised of an NMOS device having a tensile strained channel providing enhanced electron mobility, and a PMOS device having a compressively strained channel providing enhanced hole mobility.
• An SOI substrate including a gadolinium scandate dielectric layer or another rare earth scandate dielectric layer may be produced in a number of manners.
• Gadolinium scandate may be deposited by molecular beam epitaxy, in which beams of each of the elemental constituents are directed in stoichiometric amounts through an ultra-high vacuum toward a substrate where they combine chemically.
• pulsed laser deposition may be used, in which a gadolinium scandate target is vaporized by an ultraviolet laser and recrystallized on the surface of the substrate.
• Pulsed laser deposition may be preferable to molecular beam epitaxy because it is capable of producing more rapid growth.
• Chemical vapor deposition may also be used. It is notable that these methods produce a dielectric layer having a relatively smooth surface. A semiconductor layer subsequently grown on the dielectric layer has a thickness variability that is substantially less than that of layers that have been thinned by polishing.
• the rare earth scandate layer is formed on a substrate having a silicon germanium layer at its surface.
• the silicon germanium layer is typically grown on a silicon wafer in a graded fashion in which the percentage content of germanium is gradually increased from zero to a desired percent. This allows the growth of a relaxed silicon germanium layer having a desired lattice constant.
• the rare earth scandate is then formed on the silicon germanium layer such as by one of the techniques described above.
• the silicon germanium layer may be designed to have a lattice constant that matches the effective lattice constant of the rare earth scandate, or that is smaller than the effective lattice constant of the rare earth scandate so as to compress the rare earth scandate lattice and reduce its effective lattice constant.
• Figures 6a - 6f show structures formed during fabrication of a tensile strained SOI MOSFET in accordance with an exemplary embodiment of the invention.
• Figure 6a shows an SOI substrate comprising a silicon germanium layer 50.
• the silicon germanium layer 50 is typically grown on a silicon wafer, and has a graded composition with a percentage content of germanium at the surface that provides a desired lattice constant.
• the surface of the silicon germanium layer may be a relaxed silicon germanium alloy comprised of approximately 20% germanium.
• a dielectric layer 52 of a material having a perovskite lattice is formed on the silicon germanium layer 50.
• the dielectric material is a rare earth scandate such as gadolinium scandate.
• the dielectric layer 52 may be formed by various techniques such as molecular beam epitaxy, pulsed laser deposition or chemical vapor deposition.
• the gadolinium scandate layer is formed to a thickness of 100 A - 200 A.
• a semiconductor layer 54 is grown on the dielectric layer 52.
• the semiconductor layer 54 is a single crystal layer and may be composed of silicon, germanium, a silicon germanium alloy, a compound semiconductor such as a III-V or II- VI type semiconductor, or another semiconductor material having a diamond lattice.
• the thickness of the semiconductor layer may be chosen in accordance with the particular implementation.
• the semiconductor layer is a silicon layer having a thickness of approximately 200 A.
• the semiconductor layer 54 is typically undoped, however doping may be performed in accordance with the particular implementation.
• Figure 6b shows the structure of Figure 6a after selective etching of the semiconductor layer 54 to form isolated islands of semiconductor material on which individual devices will be formed.
• Figure 6c shows the structure of Figure 6b after formation of a gate insulating layer 56 over the semiconductor layer 54, followed by formation of a polysilicon gate 58 on the gate insulating layer 56.
• the gate insulating layer 56 may be grown by thermal oxidation of the semiconductor layer 54 or by deposition of a dielectric material.
• the polysilicon gate may be formed by blanket deposition of a polysilicon layer followed by patterning of the polysilicon layer.
• Figure 6d shows the structure of Figure 6c after implantation of dopant by ion implantation to form source and drain extensions 60 in the semiconductor layer 54 at opposing sides of the gate 58, followed by formation of a spacer 62 around the gate 58.
• the gate 58 masks the channel region during implantation of the source and drain extensions 60.
• the spacer 62 may be formed by blanket deposition of silicon oxide, followed by a directional etch back process to remove oxide from the horizontal surfaces.
• Figure 6e shows the structure of Figure 6d after formation of elevated source and drain regions 64 in contact with the semiconductor layer 54 at adjacent sides of the gate 58.
• the elevated source and drain regions 64 are grown by selective epitaxial growth of silicon. Typically the growth rate of silicon on the semiconductor layer 54 is significantly greater than the growth rate of silicon on the surrounding exposed dielectric layer 52.
• the atmosphere in the deposition chamber typically includes HC1, which produces a degree of etching of the deposited silicon.
• the epitaxial growth process may be optimized to produce zero net growth of silicon on the exposed portions of the dielectric layer 52. Alternatively, a brief etch-back may be performed after formation of the elevated source and drain regions 64 to remove any silicon that has accumulated on the dielectric layer 52.
• the source and drain regions 64 may be doped in situ or by an implantation process.
• Figure 6f shows the structure of Figure 6e after formation of source and drain silicides 66 and a gate silicide 68.
• the silicides 66 and 68 are formed of a compound comprising the silicon material of the gate 58 and the source and drain regions 64 and a metal such as cobalt (Co) or nickel (Ni).
• the silicides 66 and 68 are formed by depositing a thin conformal layer of the metal over the entire structure, and then annealing to promote silicide formation at the points of contact between the metal and underlying semiconductor materials, followed by stripping of residual metal. Formation of silicides is typically preceded by a patterning step to remove oxides and protective layers from portions of the source and drain regions and gate where the silicides are to be formed.
• an electronic device in accordance with an embodiment of the invention comprises a substrate that includes a layer of a dielectric material having perovskite lattice, and a layer of a single crystal semiconductor material formed on the layer of the perovskite material.
• a MOSFET incorporating the semiconductor material in its channel region may be formed on the substrate.
• the MOSFET may be structured in the manners shown herein or in a variety of other manners.
• the dielectric material and the semiconductor material may be designed to produce a desired amount of either a tensile or a compressive strain in the semiconductor material, and the strain may be directional in accordance with the shapes of faces of unit cells in the dielectric material.
• Figure 7 shows an example of elements of a CMOS device composed of first and second SOI MOSFETs formed in accordance with an embodiment of the invention.
• an n-type MOSFET device 70 incorporates a semiconductor region 72 formed on a dielectric layer 52 of a substrate.
• CMOS devices may be connected to form a CMOS device in which each device benefits from enhanced carrier mobility through the use of different silicon germanium alloys having different types of strain imparted thereto by the dielectric layer.
• the structure of Figure 7 may be fabricated in a variety of manners. Typically two independent growth steps will be performed to grow semiconductor regions having different lattice constants for the respective p-type and n-type devices. These regions may be grown in the shapes that will be utilized in the devices, or may be grown and then patterned to exact dimensions.
• a layer of one of the alloys may be grown across the wafer, and then silicon or germanium may be implanted in selected regions to alter the stoichiometric ratios in those regions to form the second alloy.
• silicon or germanium may be implanted in selected regions to alter the stoichiometric ratios in those regions to form the second alloy.
• the structure of Figure 7 utilizes two different silicon germanium alloys to produce different types of strain for nMOS and pMOS device, in alternative embodiments different types of semiconductor materials with appropriate lattice constants may be utilized. Further, dielectric material lattice properties may be designed to provide directionality of strain.
• the MOSFETs may be structured in the manners shown in Figure 7 or in a variety of other manners. The tasks described in the above processes are not necessarily exclusive of other tasks, and further tasks may be incorporated into the above processes in accordance with the particular structures to be formed.
• intermediate processing tasks such as formation or removal of passivation layers or protective layers between processing tasks, formation or removal of photoresist masks and other masking layers, doping and counter-doping, cleaning, planarization, and other tasks, may be performed along with the tasks specifically described above.
• the processes described herein need not be performed on an entire substrate such as an entire wafer, but may instead be performed selectively on sections of the substrate.
• tasks performed during the fabrication of structure described herein are shown as occurring in a particular order for purposes of example, in some instances the tasks may be performed in alternative orders while still achieving the purpose of the process.
• the embodiments illustrated in the figures and described above are presently preferred, it should be understood that these embodiments are offered by way of example only. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that fall within the scope of the claims and their equivalents.

Landscapes

• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Inorganic Insulating Materials (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Recrystallisation Techniques (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (1)

Family

ID=34964796

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (20)

Citations (7)

Family Cites Families (7)

• 2004
  • 2004-04-07 US US10/819,441 patent/US7005302B2/en not_active Expired - Lifetime
• 2005
  • 2005-03-28 DE DE112005000775T patent/DE112005000775B4/de not_active Expired - Fee Related
  • 2005-03-28 CN CN2005800183302A patent/CN1998088B/zh not_active Expired - Fee Related
  • 2005-03-28 GB GB0619840A patent/GB2429114B/en not_active Expired - Fee Related
  • 2005-03-28 WO PCT/US2005/010574 patent/WO2005101521A1/en not_active Ceased
  • 2005-03-28 JP JP2007507361A patent/JP2007533137A/ja active Pending
  • 2005-03-28 KR KR1020067023279A patent/KR101093785B1/ko not_active Expired - Fee Related
  • 2005-04-04 TW TW094110692A patent/TWI360833B/zh not_active IP Right Cessation
• 2006
  • 2006-02-24 US US11/361,207 patent/US7221025B2/en not_active Expired - Lifetime

Patent Citations (7)

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events