JP2007531309A5 - - Google Patents

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Publication number
JP2007531309A5
JP2007531309A5 JP2007506171A JP2007506171A JP2007531309A5 JP 2007531309 A5 JP2007531309 A5 JP 2007531309A5 JP 2007506171 A JP2007506171 A JP 2007506171A JP 2007506171 A JP2007506171 A JP 2007506171A JP 2007531309 A5 JP2007531309 A5 JP 2007531309A5
Authority
JP
Japan
Prior art keywords
gate electrode
electrode structure
dimension
reaction layer
process parameters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007506171A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007531309A (ja
Filing date
Publication date
Priority claimed from US10/812,952 external-priority patent/US20050221513A1/en
Application filed filed Critical
Publication of JP2007531309A publication Critical patent/JP2007531309A/ja
Publication of JP2007531309A5 publication Critical patent/JP2007531309A5/ja
Withdrawn legal-status Critical Current

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JP2007506171A 2004-03-31 2005-02-11 ゲート電極構造のトリミングを制御する方法 Withdrawn JP2007531309A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/812,952 US20050221513A1 (en) 2004-03-31 2004-03-31 Method of controlling trimming of a gate electrode structure
PCT/US2005/004915 WO2005104218A1 (en) 2004-03-31 2005-02-11 Method of controlling trimming of a gate elecrode structure

Publications (2)

Publication Number Publication Date
JP2007531309A JP2007531309A (ja) 2007-11-01
JP2007531309A5 true JP2007531309A5 (enExample) 2008-03-27

Family

ID=34960978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007506171A Withdrawn JP2007531309A (ja) 2004-03-31 2005-02-11 ゲート電極構造のトリミングを制御する方法

Country Status (5)

Country Link
US (2) US20050221513A1 (enExample)
JP (1) JP2007531309A (enExample)
KR (1) KR20060131795A (enExample)
CN (1) CN1938841A (enExample)
WO (1) WO2005104218A1 (enExample)

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WO2007095194A2 (en) * 2006-02-10 2007-08-23 Intermolecular, Inc. Method and apparatus for combinatorially varying materials, unit process and process sequence
JP2008124399A (ja) * 2006-11-15 2008-05-29 Toshiba Corp 半導体装置の製造方法
JP5229711B2 (ja) * 2006-12-25 2013-07-03 国立大学法人名古屋大学 パターン形成方法、および半導体装置の製造方法
JP4421618B2 (ja) * 2007-01-17 2010-02-24 東京エレクトロン株式会社 フィン型電界効果トランジスタの製造方法
US7674350B2 (en) * 2007-01-22 2010-03-09 Infineon Technologies Ag Feature dimension control in a manufacturing process
US20080248412A1 (en) * 2007-04-09 2008-10-09 John Douglas Stuber Supervisory etch cd control
JP5374039B2 (ja) * 2007-12-27 2013-12-25 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
JP2009289974A (ja) * 2008-05-29 2009-12-10 Toshiba Corp 半導体装置の製造方法
CN101593685B (zh) * 2008-05-29 2011-05-04 中芯国际集成电路制造(北京)有限公司 栅极形成方法
CN102194675B (zh) * 2010-03-11 2013-06-12 中芯国际集成电路制造(上海)有限公司 制作半导体器件栅极的方法
KR101145334B1 (ko) * 2010-05-31 2012-05-14 에스케이하이닉스 주식회사 반도체 장치 제조방법
CN102339772B (zh) * 2010-07-16 2014-01-15 中芯国际集成电路制造(上海)有限公司 检测通孔缺陷的方法
US20120083127A1 (en) * 2010-09-30 2012-04-05 Tokyo Electron Limited Method for forming a pattern and a semiconductor device manufacturing method
US8748199B2 (en) * 2011-04-22 2014-06-10 GlobalFoundries, Inc. In-situ measurement of feature dimensions
WO2013085290A1 (ko) * 2011-12-07 2013-06-13 주식회사 테스 반도체소자 제조방법
US9059038B2 (en) * 2012-07-18 2015-06-16 Tokyo Electron Limited System for in-situ film stack measurement during etching and etch control method
CN105493255B (zh) * 2013-08-27 2021-04-20 东京毅力科创株式会社 用于横向裁剪硬掩模的方法
US10497575B2 (en) * 2017-05-03 2019-12-03 Tokyo Electron Limited Method for increasing trench CD in EUV patterning without increasing single line opens or roughness
US10727143B2 (en) * 2018-07-24 2020-07-28 Lam Research Corporation Method for controlling core critical dimension variation using flash trim sequence
CN110687144B (zh) * 2019-10-28 2022-07-22 长江存储科技有限责任公司 一种ped样品及其制备方法
KR20230132361A (ko) * 2021-01-25 2023-09-15 램 리써치 코포레이션 열적 에칭에 의한 선택적인 실리콘 트리밍

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US5943550A (en) * 1996-03-29 1999-08-24 Advanced Micro Devices, Inc. Method of processing a semiconductor wafer for controlling drive current
US6087238A (en) * 1997-12-17 2000-07-11 Advanced Micro Devices, Inc. Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof
JP2000299367A (ja) * 1999-04-15 2000-10-24 Tokyo Electron Ltd 処理装置及び被処理体の搬送方法
US6245581B1 (en) * 2000-04-19 2001-06-12 Advanced Micro Devices, Inc. Method and apparatus for control of critical dimension using feedback etch control
US6461878B1 (en) * 2000-07-12 2002-10-08 Advanced Micro Devices, Inc. Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor
JP3708031B2 (ja) * 2001-06-29 2005-10-19 株式会社日立製作所 プラズマ処理装置および処理方法
WO2003080719A1 (en) * 2002-03-18 2003-10-02 University Of Southern California Reinforced phenolic foam

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