Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
  • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

• the present invention relates to semiconductor manufacturing, particularly to a method of controlling trimming of a gate electrode structure in a chemical trimming process
• Plasma processing systems are used in the manufacture and processing of semiconductors, integrated circuits, displays, and other devices or materials.
• Plasma processing can be used to transfer a pattern of an integrated circuit from a lithographic mask to a semiconductor substrate.
• the lithographic mask can comprise an etch-resistant photoresist layer that is deposited over a substrate, exposed to a selected lithographic pattern and developed.
• the lithographic mask structure can include additional mask layers, e.g., anti-reflective coatings (ARCs). ARC layers are frequently used to reduce light reflections from the substrate during lithography steps, and sacrificial masks can be used to pattern areas on a substrate.
• ARCs anti-reflective coatings
• a critical dimension (CD) of a circuit is the width of a line or space that has been identified as critical to the device being fabricated to operate properly and it further determines the device performance.
• CD-bias The reduction in CD during the plasma etching process.
• CD-bias a consequence of plasma PR-trim process is iso-dense CD-bias, which is the difference between the CDs of dense (closely spaced) and isolated structures, while keeping all other processing parameters (e.g., focus and exposure) constant. This is due to the nature of the neutral-dominant isotropic etching process.
• the present invention provides a method of trimming a gate electrode structure by determining a first dimension of the gate electrode structure, choosing a target trimmed dimension, feeding forward the first dimension and the target trimmed dimension to a process model to create a set of process parameters, and performing a trimming process on the gate electrode structure, including controlling the set of process parameters in the trimming process, and trimming the gate electrode structure.
• the trimming process may be repeated at least once until the target trimmed dimension is obtained, where the trimmed dimension may be fed backward to the process model to create a new set of process parameters.
• a processing tool is provided for trimming a gate electrode structure.
• the processing tool contains a substrate loading chamber configured for loading and unloading a substrate with a gate electrode structure having a first dimension, a transfer system configured for transferring the substrate within the processing tool, at least one processing system configured for performing a trimming process on the gate electrode structure to form a trimmed dimension, at least one controller configured for storing a process model capable of creating a set of process parameters from the first dimension and a target trimmed dimension, and controlling the set of process parameters in the trimming process, and a further processing system for measuring at least one of the first dimension and the trimmed dimension of the gate electrode structure.
• FIGS. 1 A-1 G show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to an embodiment of the invention
• FIG. 2 schematically shows reaction layer thickness as a function of reactant gas exposure according to an embodiment of the invention
• FIGS. 3A-3C show a schematic cross-sectional representation of a process flow for trimming gate electrode structure according to another embodiment of the invention
• FIGS. 4A-4B show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to yet another embodiment of the invention
• FIGS. 5A-5D show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to still another embodiment of the invention
• FIG. 6 is a flowchart for trimming a gate electrode structure according to an embodiment of the invention.
• FIG. 7 is a flowchart for controlling trimming of a gate electrode structure according to an embodiment of the invention.
• FIG. 8 schematically shows a processing tool for trimming a gate electrode structure according to an embodiment of the invention;
• FIG. 9 is a depiction of a general purpose computer which may be used to implement the present invention.
• DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS [0020]
• FIGS. 1A-1G show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to an embodiment of the invention. Utilizing a soft-mask processing scheme, a dimension of a lithographically patterned gate electrode structure is trimmed by a chemical etching process. The dimension after trimming can be below the lithographic dimension of the photoresist pattern, or it can be any dimension.
• FIG. 1A shows a gate electrode structure 10 containing a substrate 100, a high-k layer 102, a gate electrode layer 104, an organic ARC layer 106, and a patterned photoresist layer 108.
• the gate electrode layer 104 can be a Si-containing layer, e.g., amorphous Si, poly-Si, or SiGe or any combination thereof.
• the gate electrode layer 104 can be a metal-containing layer, for example a metal (e.g., Ru), a metal alloy (e.g., TiNi), a metal nitride (e.g., TaN, TaSiN, TiN, HfN), or a metal oxide (e.g., Ru0 2 ) or any combination thereof.
• the high-k layer 102 can, for example, contain Hf0 2 , HfSiO x , Zr0 2 , or ZrSiOx or a combination of two or more thereof.
• the patterned photoresist layer 108 can be formed by exposing a photoresist layer to light through a mask, and then removing the unexposed areas with a developer solution.
• the resulting patterned photoresist layer 108 in FIG. 1A, with an initial lithographic dimension 122, can be used to transfer the lithographic pattern to the underlying layers 104 and 106 using an anisotropic etch process such as Reactive Ion Etching (RIE).
• RIE Reactive Ion Etching
• the etching of the gate electrode layer 104 and the organic ARC layer 106 can be carried out using wide variety of well-known etch gases.
• the etch gases can, for example, contain Cl 2 , HBr, HCI, CF , SF ⁇ , C 2 F 6 , or NF 3 or any combination of two or more thereof.
• the gate electrode structure 10, shown in FIG. 1A can require an etch process of about 4 min to form the gate electrode structure 10 shown in FIG. 1B.
• the etch process creates a small CD-bias corresponding to the difference between the initial lithographic dimension 122 and the first horizontal dimension 120 in the photoresist layer 108, the organic ARC layer 106, and the gate electrode layer 104, as shown in FIG. 1 B.
• the photoresist layer 108 and the organic ARC layer 106 can be removed before the chemical trimming process is carried out, as shown in FIG. 1C, or alternately, the photoresist layer 108 and the organic ARC layer 106 can be used to protect the horizontal (top) surface of the gate electrode layer 104 during the trimming process.
• the gate electrode layer 104 is characterized by the first horizontal dimension 120 and a first vertical dimension 122.
• a chemical trimming process can further reduce the CD (first horizontal dimension 118, see FIG. 1 D) below the lithographical dimension 120, without changing the iso-dense CD-bias or the profile (maybe a little change on profile) of the gate electrode layer 104.
• the gate electrode structure 10 in FIG. 1C can be exposed to a reactant gas that reacts isotropically with the gate electrode structure 10 to form the reaction layer 104b shown in FIG. 1 D.
• the reactant gas can be exposed to the gate electrode structure in a thermal process or in a plasma process.
• the thickness of the reaction layer 104b depends on the process conditions, e.g., the type of reactant gas, reactant gas pressure, exposure time, and substrate temperature. Formation of the reaction layer 104b hinders further reaction between the remaining gate electrode layer 104a and the reactant gas by acting as a physical diffusion barrier.
• the gate electrode structure 10 is exposed to the reactant gas for a time period that enables formation of a reaction layer 104b with a desired thickness.
• FIG. 2 schematically shows reaction layer thickness as a function of reactant gas exposure time according to an embodiment of the invention.
• Curves 200-220 show different reaction layer thicknesses for different processing conditions. As seen in FIG. 2, a rapid increase in reaction layer thickness can be initially observed, followed by a "flattening out” of the rate of increase with increasing exposure time. The “flattening out” is due to a self- limiting reaction, where the thickness of the reaction layer approaches an asymptotic value.
• process conditions are selected that form a reaction layer with the required control and repeatability, on a timescale that is practical for semiconductor manufacturing. Different trimming recipes can thus be developed that yield different reaction layer thicknesses and allow good repeatable control over the trimming process.
• a Si0 2 reaction layer 104b with a thickness between about 2 nm to about 5 nm can be formed on a time scale that is practical for manufacturing semiconductor devices, e.g., between about 10 and about 30 sec, depending on the plasma processing conditions and the substrate temperature.
• a reactant gas containing excited oxygen species is used to react with a poly-Si gate electrode layer to form a Si0 2 reaction layer 104b.
• the excited oxygen species can be produced using an 0 2 plasma source.
• the 0 2 plasma source can be a remote plasma source if the source needs to be removed from the substrate in the processing system.
• an oxygen-containing gas such as 0 2 or H 2 0, may be used to thermally oxidize a poly-Si gate electrode to form a Si0 2 reaction layer.
• a wet oxidation process may be used. The oxidizing process may, for example, immerse the substrate in warm H 2 0 or an acidic solution.
• the 0 2 plasma processing conditions and the substrate temperature were selected to yield about a 4 nm thick Si0 2 reaction layer 104b in about 15 sec, on both isolated and dense gate electrode structures.
• the thickness of the Si0 2 reaction layer 104 appeared to be saturated at room temperature after about 15 sec, and longer exposure times did not result in increased thickness of the reaction layer 104b.
• the short processing times for forming a Si0 2 reaction layer 104b allows for the required high substrate through-put.
• the exposure of the gate electrode structure 10 to the reactant gas is stopped. Thereafter, the reaction layer 104b is removed (stripped) from the unreacted gate electrode layer 104a.
• the reaction layer 104b can, for example, be removed by exposing the gate electrode structure 10 to an etch gas. Choosing an etch gas that is capable of removing the reaction layer 104b can depend on the gate electrode material. Removal of the reaction layer 104b is selective to unreacted gate electrode material and results in a trimmed gate electrode layer 104a shown in FIG. 1 E.
• the etch gas can, for example be aqueous HF vapor (HF( aq )).
• HF( aq ) has high etch selectivity for Si0 2 over Si, allowing fast, selective removal of the Si0 2 reaction layer 104b from the remaining Si gate electrode layer 104a.
• the exposure of the Si0 2 reaction layer 104b to the HF( aq ) etch gas can be carried out for a predetermined time period that is sufficiently long to complete the removal of the Si0 2 reaction layer 104b.
• a 4 nm thick Si0 2 reaction layer 104b can be removed in about 10 sec.
• the trimmed gate electrode layer 104a is characterized by a second horizontal dimension 118 and a second vertical dimension 124 that are smaller than the first horizontal dimension 120 and the first vertical dimension 122 in FIG.
• the trimming process can be repeated if it is desired to further trim the gate electrode layer 104a. Repeating the trimming process forms a reaction layer 104d in FIG. 1 F, and a trimmed gate electrode layer 104c with new dimensions 116 and 126 in FIG. 1G.
• Another example to trim away oxidized film 104a is to use COR (chemical oxide removal). Etch gases HF and NH 3 are used to react with the oxide film and then heat treatment is used to evaporate the trimmed product.
• Another COR example is to use NF 3 and NH 3 etch gases excited by a remote plasma source.
• Still another COR example is to use NH 4 F vapor to thermally react with the oxide film.
• Another example to trim away oxidized film 104a is to use a wet process. The wet process may, for example, immerse the substrate in a buffered HF solution.
• a trimming cycle includes forming a reaction layer and removing the reaction layer.
• a trimming cycle reduces the first horizontal dimension 120 of the gate electrode layer 104 twice as much as the first vertical dimension 122.
• one trimming cycle can reduce the horizontal dimension 120 of a Si gate electrode layer 104 by about 8 nm and vertical dimension by about 4 nm.
• the first vertical dimension 120 can be about 120 nm and the first vertical dimension 122 can be about 140 nm.
• a trimming process containing 10 trimming cycles can reduce the first horizontal dimension 120 to about 40 nm and the first vertical dimension 122 to about 100 nm.
• FIG. 3A-3C show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to another embodiment of the invention.
• a metal-containing layer 103 is inserted between gate electrode layer 104 and the dielectric layer 102.
• the metal-containing layer 103 can, for example, be selected from TaN, TiN, TaSiN, Ru, or Ru0 2 materials or any combinations thereof.
• the high-k layer 102 can, for example, contain Hf0 2 , HfSiO x , Zr0 2 , or ZrSiO x or any combination of two or more thereof. Trimming of the gate electrode layer 104 can be carried out as described above in FIGS.
• the trimmed gate electrode layer 104c can be used as a mask layer in an anisotropic etch process to define sub-lithographic etch features in the metal-containing layer 103, as shown in FIG. 3C.
• Etching of the metal- containing layer 103 reduces the dimension 126 of the gate electrode layer 104c according to the etch ratio of these layers.
• the etch ratio can be about 1.5 (poly-Si/TiN).
• the dimension 126 can be selected based on the etch ratio of layers 104 and 103.
• TaN, TiN, and TaSiN materials can be plasma etched using halogen-based gases, for example Cl 2 .
• a Ru-containing material can, for example, be plasma etched using 0 2 and Cl 2 gas mixture.
• an inorganic ARC layer can be used to prevent reducing the dimension 126 while etching the metal containing layer 103.
• FIGS. 4A-4B show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to yet another embodiment of the invention.
• the gate electrode structure 10 in FIG. 4A contains an inorganic ARC layer 106 that is trimmed along with the gate electrode layer 104 to form a trimmed gate electrode structure 10 in FIG. 4B.
• the inorganic ARC layer 106 can, for example, contain SiN, and the dielectric layer 102 can be selected from Si0 2 , SiO x N y , or high-k materials such as Hf0 2 , HfSiO x , Zr0 2 , or ZrSiO x .
• Trimming of a SiN ARC layer 106 and a poly-Si gate electrode layer 104 can be performed by exposing the gate electrode structure 10 to excited oxygen species in an 0 2 plasma.
• the growth rate of a reaction layer can vary on the SiN ARC layer and the poly-Si gate electrode layer, but the asymptotic reaction layer thickness is expected be similar on the SiN and poly-Si materials.
• FIGS. 5A-5D show a schematic cross-sectional representation of a process flow for trimming a gate electrode structure according to still another embodiment of the invention.
• the gate electrode structure 10 contains a substrate 100, a dielectric layer 102, a gate electrode layer 104, an inorganic ARC layer 106, and a patterned photoresist layer 108.
• the inorganic ARC layer 106 can, for example, contain SiN, and the dielectric layer 102 can be selected from Si0 2 , SiO x N y , and high-k materials such as Hf0 2 , HfSiO x , Zr0 2 , and ZrSiO x .
• FIG. 6 is a flow-chart for trimming a gate electrode structure according to an embodiment of the invention.
• the process is started.
• a gate electrode structure containing a gate electrode layer with a first dimension is provided in a processing system.
• a trimming recipe is selected. A trimming recipe is selected that enables the desired trimming of the gate electrode structure.
• a reaction layer is formed through reaction with the gate electrode structure.
• the reaction layer can be formed by exposing the gate electrode structure a reactant gas in a thermal process or in a plasma process.
• the reaction layer is removed from the unreacted portion of the gate electrode structure, thereby forming a gate electrode structure having a second dimension that is smaller than the first dimension.
• the reaction layer can be removed by exposed it to an etch gas capable of selectively etching the reaction layer.
• a method is provided for controlling trimming of a gate electrode structure using a process model.
• the process model contains a set of process parameters that are used by a processing system to trim a dimension of the gate electrode structure in a trimming process.
• the process model can utilize a mathematical function to characterize the relationship between the process parameters and the reaction layer thickness.
• the function f(x) can, for example, be a linear function or a quadratic function.
• the set of process parameters can, for example, include process gas pressure, substrate temperature, plasma power, and process time.
• the relationship between the process parameters and the reaction layer thickness in equation (1) is called a trim curve.
• a trim curve can be chosen that contains a single variable process parameter and other process parameters are kept constant.
• a single variable process parameter for example process gas pressure
• a cluster of pressure trim curves can be obtained by varying at least one additional process parameter, e.g., plasma power.
• a cluster of available pressure trim curves can provide more process flexibility and reduce constraints on process operating conditions such as pressure control limit, power limit, gas flow controller resolution.
• a process model containing a group of trim curves can be created by performing multiple trimming processes and correlating the different process parameters with the resulting reaction layer thickness and trim amount. The process model may then be used to control the set of process parameter according to the target reaction layer thickness, as shown in equation (3):
• the first dimension of the gate electrode structure can be an initial critical dimension CD 0 (e.g., dimension 120 in FIG. 1C) and the target trimmed dimension can be a target critical dimension CD t (e.g., dimension 118 in FIG. 1E or dimension 116 in FIG. 1G).
• the target reaction layer thickness is greater than the reaction layer thickness by an amount greater than what can be achieved in a single trimming process, it may be necessary to perform multiple trimming processes.
• the multiple trimming processes may be selected to yield the same reaction layer thickness or, alternatively, they may be selected to yield different reaction layer thicknesses.
• FIG. 7 is a flowchart for controlling trimming of a gate electrode structure according to an embodiment of the invention.
• the process is started.
• a first dimension of the gate electrode structure is measured in a pre-trimming metrology step.
• the first dimension and a target trimmed dimension are fed forward to a process model 766 to create a set of process parameters according to the first dimension and the target trimmed dimension.
• a trimming process is performed at 768 according to the process model to form a trimmed gate electrode structure having a trimmed dimension that is smaller than the first dimension.
• the trimmed dimension is measured in a post-trimming metrology step at 770.
• trimming process 768 may be repeated at least once until the target trimmed dimension is obtained.
• the repeating may further include feeding backward the trimmed dimension to the process model 766 to create a new set of process parameters.
• the trimming process may be carried out multiple times until the target trimmed dimension is obtained, where a new set of process parameters may be created before each trimming process is performed.
• the process ends at 768.
• FIG. 8 schematically shows a processing tool for trimming a gate electrode structure according to an embodiment of the invention.
• the processing tool 800 can, for example, be a UnityMe etch tool from Tokyo Electron Limited, Akasaka, Japan.
• the processing tool 800 contains substrate loading chambers 810 and 820, processing systems 830 - 860, robotic transfer system 870, and controller 880.
• plasma etching of a photoresist layer 108, an ARC layer 106, a gate electrode layer 104 (e.g., see FIG. 1), and a metal-containing layer 103 (e.g., see FIG. 3) can be performed in the processing system 840.
• formation of a reaction layer through exposure of a gate electrode structure to a reactant gas can be performed in processing system 850, and the removal of the reaction layer 104b through exposure to an etch gas can be performed in processing system 860.
• the formation and removal of the reaction layer 104b can be carried out in a single processing system as described above or, alternately, in different processing systems.
• the use of multiple processing systems to perform a trimming cycle can be advantageous when the trimming process includes corrosive gaseous reactants that are difficult to evacuate from a processing system following a gas exposure.
• a high background pressure containing corrosive gaseous reactants can result in continued reaction with the gate electrode layer and can erode the semiconductor substrate.
• the processing system 830 can be used as an analysis chamber for determining a dimension of a gate electrode structure. Based on the measured dimension, a decision can be made to perform another trimming cycle, using the same or another trimming recipe, or to stop the trimming process.
• the processing system 830 can, for example, be an Optical Digital Profilometer (ODPTM) from TIMBRE Technologies, Santa Clara, CA, or a scanning electron microscope (SEM).
• ODPTM Optical Digital Profilometer
• SEM scanning electron microscope
• the processing tool 800 can be controlled by a controller 880.
• the controller 880 can be coupled to and exchange information with substrate loading chambers 810 and 820, processing systems 830-860, and robotic transfer system 870.
• a program stored in the memory of the controller 880 can be utilized to control the aforementioned components of the processing 800 according to a desired process, and to perform any functions associated with monitoring the process.
• the controller 880 can furthermore store a process model for creating a set of process parameters for performing a trimming process in the processing tool 800.
• FIG. 9 illustrates a computer system 1201 upon which an embodiment of the present invention may be implemented.
• the computer system 1201 may be used as the controller of FIG. 8, or a similar controller that may be used to perform any or all of the functions described above.
• the computer system 1201 includes a bus 1202 or other communication mechanism for communicating information, and a processor 1203 coupled with the bus 1202 for processing the information.
• the computer system 1201 also includes a main memory 1204, such as a random access memory (RAM) or other dynamic storage device (e.g., dynamic RAM (DRAM), static RAM (SRAM), and synchronous DRAM (SDRAM)), coupled to the bus 1202 for storing information and instructions to be executed by processor 1203.
• main memory 1204 may be used for storing temporary variables or other intermediate information during the execution of instructions by the processor 1203.
• the computer system 1201 further includes a read only memory (ROM) 1205 or other static storage device (e.g., programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM)) coupled to the bus 1202 for storing static information and instructions for the processor 1203.
• ROM read only memory
• PROM programmable ROM
• EPROM erasable PROM
• EEPROM electrically erasable PROM
• the computer system 1201 also includes a disk controller 1206 coupled to the bus 1202 to control one or more storage devices for storing information and instructions, such as a magnetic hard disk 1207, and a removable media drive 1208 (e.g., floppy disk drive, read-only compact disc drive, read/write compact disc drive, compact disc jukebox, tape drive, and removable magneto-optical drive).
• the storage devices may be added to the computer system 1201 using an appropriate device interface (e.g., small computer system interface (SCSI), integrated device electronics (IDE), enhanced-IDE (E-IDE), direct memory access (DMA), or ultra-DMA).
• SCSI small computer system interface
• IDE integrated device electronics
• E-IDE enhanced-IDE
• DMA direct memory access
• ultra-DMA ultra-DMA
• the computer system 1201 may also include special purpose logic devices (e.g., application specific integrated circuits (ASICs)) or configurable logic devices (e.g., simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs)).
• ASICs application specific integrated circuits
• SPLDs simple programmable logic devices
• CPLDs complex programmable logic devices
• FPGAs field programmable gate arrays
• the computer system may also include one or more digital signal processors (DSPs) such as the TMS320 series of chips from Texas Instruments, the DSP56000, DSP56100, DSP56300, DSP56600, and DSP96000 series of chips from Motorola, the DSP1600 and DSP3200 series from Lucent Technologies or the ADSP2100 and ADSP21000 series from Analog Devices.
• DSPs digital signal processors
• the computer system may also include one or more digital signal processors (DSPs) such as the TMS320 series of chips from Texas Instruments, the DSP56000, DSP56100, DSP56300, DSP56600, and DSP96000 series of chips from Motorola, the DSP1600 and DSP3200 series from Lucent Technologies or the ADSP2100 and ADSP21000 series from Analog Devices.
• DSPs digital signal processors
• Other processors specially designed to process analog signals that have been converted to the digital domain may also be used.
• the computer system 1201 may also include a display controller 1209 coupled to the bus 1202 to control a display 1210, such as a cathode ray tube (CRT), for displaying information to a computer user.
• the computer system includes input devices, such as a keyboard 1211 and a pointing device 1212, for interacting with a computer user and providing information to the processor 1203.
• the pointing device 1212 for example, may be a mouse, a trackball, or a pointing stick for communicating direction information and command selections to the processor 1203 and for controlling cursor movement on the display 1210.
• a printer may provide printed listings of data stored and/or generated by the computer system 1201.
• the computer system 1201 performs a portion or all of the processing steps of the invention in response to the processor 1203 executing one or more sequences of one or more instructions contained in a memory, such as the main memory 1204. Such instructions may be read into the main memory 1204 from another computer readable medium, such as a hard disk 1207 or a removable media drive 1208.
• processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory 1204.
• hard-wired circuitry may be used in place of or in combination with software instructions. Thus, embodiments are not limited to any specific combination of hardware circuitry and software.
• the computer system 1201 includes at least one computer readable medium or memory for holding instructions programmed according to the teachings of the invention and for containing data structures, tables, records, or other data described herein.
• Examples of computer readable media are compact discs, hard disks, floppy disks, tape, magneto- optical disks, PROMs (EPROM, EEPROM, flash EPROM), DRAM, SRAM, SDRAM, or any other magnetic medium, compact discs (e.g., CD-ROM), or any other optical medium, punch cards, paper tape, or other physical medium with patterns of holes, a carrier wave (described below), or any other medium from which a computer can read.
• the present invention includes software for controlling the computer system 1201 , for driving a device or devices for implementing the invention, and for enabling the computer system 1201 to interact with a human user (e.g., print production personnel).
• software may include, but is not limited to, device drivers, operating systems, development tools, and applications software.
• Such computer readable media further includes the computer program product of the present invention for performing all or a portion (if processing is distributed) of the processing performed in implementing the invention.
• the computer code devices of the present invention may be any interpretable or executable code mechanism, including but not limited to scripts, interpretable programs, dynamic link libraries (DLLs), Java classes, and complete executable programs. Moreover, parts of the processing of the present invention may be distributed for better performance, reliability, and/or cost.
• Non-volatile media includes, for example, optical, magnetic disks, and magneto-optical disks, such as the hard disk 1207 or the removable media drive 1208.
• Volatile media includes dynamic memory, such as the main memory 1204.
• Transmission media includes coaxial cables, copper wire and fiber optics, including the wires that make up the bus 1202. Transmission media also may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.
• Various forms of computer readable media may be involved in carrying out one or more sequences of one or more instructions to processor 1203 for execution.
• the instructions may initially be carried on a magnetic disk of a remote computer.
• the remote computer can load the instructions for implementing all or a portion of the present invention remotely into a dynamic memory and send the instructions over a telephone line using a modem.
• a modem local to the computer system 1201 may receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal.
• An infrared detector coupled to the bus 1202 can receive the data carried in the infrared signal and place the data on the bus 1202.
• the bus 1202 carries the data to the main memory 1204, from which the processor 1203 retrieves and executes the instructions.
• the instructions received by the main memory 1204 may optionally be stored on storage device 1207 or 1208 either before or after execution by processor 1203.
• the computer system 1201 also includes a communication interface 1213 coupled to the bus 1202.
• the communication interface 1213 provides a two-way data communication coupling to a network link 1214 that is connected to, for example, a local area network (LAN) 1215, or to another communications network 1216 such as the Internet.
• LAN local area network
• the communication interface 1213 may be a network interface card to attach to any packet switched LAN.
• the communication interface 1213 may be an asymmetrical digital subscriber line (ADSL) card, an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of communications line. Wireless links may also be implemented.
• the communication interface 1213 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.
• the network link 1214 typically provides data communication through one or more networks to other data devices.
• the network link 1214 typically provides data communication through one or more networks to other data devices.
• the network link 1214 typically provides data communication through one or more networks to other data devices.
• the local network 1214 and the communications network 1216 use, for example, electrical, electromagnetic, or optical signals that carry digital data streams, and the associated physical layer (e.g., CAT 5 cable, coaxial cable, optical fiber, etc).
• the signals through the various networks and the signals on the network link 1214 and through the communication interface 1213, which carry the digital data to and from the computer system 1201 maybe implemented in baseband signals, or carrier wave based signals.
• the baseband signals convey the digital data as unmodulated electrical pulses that are descriptive of a stream of digital data bits, where the term "bits" is to be construed broadly to mean symbol, where each symbol conveys at least one or more information bits.
• the digital data may also be used to modulate a carrier wave, such as with amplitude, phase and/or frequency shift keyed signals that are propagated over a conductive media, or transmitted as electromagnetic waves through a propagation medium.
• the digital data may be sent as unmodulated baseband data through a "wired" communication channel and/or sent within a predetermined frequency band, different than baseband, by modulating a carrier wave.
• the computer system 1201 can transmit and receive data, including program code, through the network(s) 1215 and 1216, the network link 1214, and the communication interface 1213.
• the network link 1214 may provide a connection through a LAN 1215 to a mobile device 1217 such as a personal digital assistant (PDA) laptop computer, or cellular telephone.
• PDA personal digital assistant
• the computer system 1201 may be configured to perform the method of the present invention to fabricate semiconductor device by performing a trimming process on a gate electrode structure.
• the computer system 1201 may be configured to create a set of process parameters utilizing a process model and controlling the trimming process.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Electrodes Of Semiconductors (AREA)
• Drying Of Semiconductors (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2004
  • 2004-03-31 US US10/812,952 patent/US20050221513A1/en not_active Abandoned
• 2005
  • 2005-02-11 JP JP2007506171A patent/JP2007531309A/ja not_active Withdrawn
  • 2005-02-11 KR KR1020067013196A patent/KR20060131795A/ko not_active Withdrawn
  • 2005-02-11 WO PCT/US2005/004915 patent/WO2005104218A1/en not_active Ceased
  • 2005-02-11 CN CNA2005800100314A patent/CN1938841A/zh active Pending
• 2007
  • 2007-01-11 US US11/652,074 patent/US20070111338A1/en not_active Abandoned

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