JP2007531309A - ゲート電極構造のトリミングを制御する方法 - Google Patents

ゲート電極構造のトリミングを制御する方法 Download PDF

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Publication number
JP2007531309A
JP2007531309A JP2007506171A JP2007506171A JP2007531309A JP 2007531309 A JP2007531309 A JP 2007531309A JP 2007506171 A JP2007506171 A JP 2007506171A JP 2007506171 A JP2007506171 A JP 2007506171A JP 2007531309 A JP2007531309 A JP 2007531309A
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Japan
Prior art keywords
gate electrode
electrode structure
layer
dimension
processing tool
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Withdrawn
Application number
JP2007506171A
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English (en)
Japanese (ja)
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JP2007531309A5 (enExample
Inventor
ホンギュ・ユエ
リー・チェン
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2007531309A publication Critical patent/JP2007531309A/ja
Publication of JP2007531309A5 publication Critical patent/JP2007531309A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2007506171A 2004-03-31 2005-02-11 ゲート電極構造のトリミングを制御する方法 Withdrawn JP2007531309A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/812,952 US20050221513A1 (en) 2004-03-31 2004-03-31 Method of controlling trimming of a gate electrode structure
PCT/US2005/004915 WO2005104218A1 (en) 2004-03-31 2005-02-11 Method of controlling trimming of a gate elecrode structure

Publications (2)

Publication Number Publication Date
JP2007531309A true JP2007531309A (ja) 2007-11-01
JP2007531309A5 JP2007531309A5 (enExample) 2008-03-27

Family

ID=34960978

Family Applications (1)

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JP2007506171A Withdrawn JP2007531309A (ja) 2004-03-31 2005-02-11 ゲート電極構造のトリミングを制御する方法

Country Status (5)

Country Link
US (2) US20050221513A1 (enExample)
JP (1) JP2007531309A (enExample)
KR (1) KR20060131795A (enExample)
CN (1) CN1938841A (enExample)
WO (1) WO2005104218A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013085290A1 (ko) * 2011-12-07 2013-06-13 주식회사 테스 반도체소자 제조방법
JP2016529736A (ja) * 2013-08-27 2016-09-23 東京エレクトロン株式会社 ハードマスクを横方向にトリミングする方法
JP2024503562A (ja) * 2021-01-25 2024-01-26 ラム リサーチ コーポレーション 熱エッチングによる選択的ケイ素トリミング

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101388389B1 (ko) * 2006-02-10 2014-04-22 인터몰레큘러 인코퍼레이티드 재료, 단위 프로세스 및 프로세스 시퀀스를 조합적으로 변경하는 방법 및 장치
JP2008124399A (ja) * 2006-11-15 2008-05-29 Toshiba Corp 半導体装置の製造方法
JP5229711B2 (ja) * 2006-12-25 2013-07-03 国立大学法人名古屋大学 パターン形成方法、および半導体装置の製造方法
JP4421618B2 (ja) * 2007-01-17 2010-02-24 東京エレクトロン株式会社 フィン型電界効果トランジスタの製造方法
US7674350B2 (en) * 2007-01-22 2010-03-09 Infineon Technologies Ag Feature dimension control in a manufacturing process
US20080248412A1 (en) * 2007-04-09 2008-10-09 John Douglas Stuber Supervisory etch cd control
JP5374039B2 (ja) * 2007-12-27 2013-12-25 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
US8168542B2 (en) * 2008-01-03 2012-05-01 International Business Machines Corporation Methods of forming tubular objects
US8012811B2 (en) * 2008-01-03 2011-09-06 International Business Machines Corporation Methods of forming features in integrated circuits
CN101593685B (zh) * 2008-05-29 2011-05-04 中芯国际集成电路制造(北京)有限公司 栅极形成方法
JP2009289974A (ja) * 2008-05-29 2009-12-10 Toshiba Corp 半導体装置の製造方法
CN102194675B (zh) * 2010-03-11 2013-06-12 中芯国际集成电路制造(上海)有限公司 制作半导体器件栅极的方法
KR101145334B1 (ko) * 2010-05-31 2012-05-14 에스케이하이닉스 주식회사 반도체 장치 제조방법
CN102339772B (zh) * 2010-07-16 2014-01-15 中芯国际集成电路制造(上海)有限公司 检测通孔缺陷的方法
US20120083127A1 (en) * 2010-09-30 2012-04-05 Tokyo Electron Limited Method for forming a pattern and a semiconductor device manufacturing method
US8748199B2 (en) * 2011-04-22 2014-06-10 GlobalFoundries, Inc. In-situ measurement of feature dimensions
US9059038B2 (en) * 2012-07-18 2015-06-16 Tokyo Electron Limited System for in-situ film stack measurement during etching and etch control method
US10497575B2 (en) * 2017-05-03 2019-12-03 Tokyo Electron Limited Method for increasing trench CD in EUV patterning without increasing single line opens or roughness
US10727143B2 (en) * 2018-07-24 2020-07-28 Lam Research Corporation Method for controlling core critical dimension variation using flash trim sequence
CN110687144B (zh) * 2019-10-28 2022-07-22 长江存储科技有限责任公司 一种ped样品及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US5943550A (en) * 1996-03-29 1999-08-24 Advanced Micro Devices, Inc. Method of processing a semiconductor wafer for controlling drive current
US6087238A (en) * 1997-12-17 2000-07-11 Advanced Micro Devices, Inc. Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof
JP2000299367A (ja) * 1999-04-15 2000-10-24 Tokyo Electron Ltd 処理装置及び被処理体の搬送方法
US6245581B1 (en) * 2000-04-19 2001-06-12 Advanced Micro Devices, Inc. Method and apparatus for control of critical dimension using feedback etch control
US6461878B1 (en) * 2000-07-12 2002-10-08 Advanced Micro Devices, Inc. Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor
JP3708031B2 (ja) * 2001-06-29 2005-10-19 株式会社日立製作所 プラズマ処理装置および処理方法
AU2003225852A1 (en) * 2002-03-18 2003-10-08 University Of Southern California Reinforced phenolic foam

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013085290A1 (ko) * 2011-12-07 2013-06-13 주식회사 테스 반도체소자 제조방법
JP2016529736A (ja) * 2013-08-27 2016-09-23 東京エレクトロン株式会社 ハードマスクを横方向にトリミングする方法
JP2024503562A (ja) * 2021-01-25 2024-01-26 ラム リサーチ コーポレーション 熱エッチングによる選択的ケイ素トリミング

Also Published As

Publication number Publication date
CN1938841A (zh) 2007-03-28
US20050221513A1 (en) 2005-10-06
WO2005104218A1 (en) 2005-11-03
KR20060131795A (ko) 2006-12-20
US20070111338A1 (en) 2007-05-17

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