JP5264834B2 - エッチング方法及び装置、半導体装置の製造方法 - Google Patents
エッチング方法及び装置、半導体装置の製造方法 Download PDFInfo
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Description
22…排気口
12…サセプタ(載置台)
54…スロットアンテナ
60…マイクロ波発生器
58…マイクロ波導入路58
82…処理ガス供給源
88…第一のガス導入部
94…第二のガス導入部
203…PMOSトランジスタ
204…NMOSトランジスタ
220…窒化シリコン膜
222…酸化シリコン膜
225…堆積物
301…ゲート電極
303…酸化シリコン膜
303a…オフセットスペーサ
305,308…堆積物
307…窒化シリコン膜
307…窒化シリコン膜
307a…サイドウォールスペーサ
308…堆積物
W…シリコン基板(基板)
Claims (13)
- 基板の下地膜上に形成された絶縁膜をエッチングする方法であって、
前記絶縁膜をプラズマ化させた炭素、フッ素、酸素及び水素を含む第一の処理ガスに晒し、前記絶縁膜を厚さ方向に途中までエッチングすると共に、前記絶縁膜上に堆積物を生成する第一のエッチング工程と、
前記第一のエッチング工程の終了後、前記堆積物を酸素プラズマに晒し、前記酸素プラズマにより前記堆積物を除去する堆積物除去工程と、
前記残存する絶縁膜をプラズマ化させた炭素、フッ素、酸素及び水素を含む第二の処理ガスに晒し、前記残存する絶縁膜をエッチングする第二のエッチング工程と、を備えるエッチング方法。 - 前記第二のエッチング工程の処理時間は、前記第一のエッチング工程の処理時間より短いことを特徴とする請求項1に記載のエッチング方法。
- 前記第一のエッチング工程及び前記第二のエッチング工程では、前記基板にバイアスを印加することを特徴とする請求項1又は2に記載のエッチング方法。
- 前記炭素、フッ素、及び水素を含むガスは、CHF 3 、CH 2 F 2 、及びCH 3 Fの一つであることを特徴とする請求項1ないし3のいずれか1項に記載のエッチング方法。
- 前記酸素を含むガスは、O 2 、COの1つであることを特徴とする請求項1ないし4のいずれか1項に記載のエッチング方法。
- 前記絶縁膜は、窒化シリコン膜の上に積層された酸化シリコン膜であり、
前記第一及び前記第二のエッチング工程では、前記酸化シリコン膜をエッチングすることを特徴とする請求項1ないし5のいずれかに記載のエッチング方法。 - 前記エッチング方法はさらに、前記窒化シリコン膜をエッチングする窒化シリコン膜エッチング工程を備えることを特徴とする請求項6に記載のエッチング方法。
- 前記エッチング方法は、基板上に形成されるNチャネル型FET(Field Effect Transistor)及びPチャネル型FETの少なくとも一方に応力を与える応力誘起層を形成するためのエッチング方法であることを特徴とする請求項1ないし7のいずれかに記載のエッチング方法。
- 前記基板は、シリコン基板であり、
前記絶縁膜は、前記シリコン基板の上に形成される酸化シリコン膜であり、
前記エッチング方法は、前記ゲート電極の側壁にオフセットスペーサ又はサイドウォールスペーサを形成するためのエッチング方法であることを特徴とする請求項1ないし8のいずれか1項に記載のエッチング方法。 - 前記堆積物除去工程を行うときの前記処理容器の圧力が、100mTorr(13.33Pa)以上であることを特徴とする請求項1ないし9のいずれか1項に記載のエッチング方法。
- 前記第一のエッチング工程、前記堆積物除去工程、及び前記第二のエッチング工程が同一の処理容器内で行われることを特徴とする請求項1ないし10のいずれか1項に記載のエッチング方法。
- 天井部にマイクロ波を透過する誘電体窓を有すると共に、内部を気密に保つことが可能な処理容器と、
前記処理容器の内部に設けられ、基板を載置する載置台と、
前記処理容器の前記誘電体窓の上面に設けられ、前記処理容器の処理空間に多数のスロットを介してマイクロ波を導入するスロットアンテナと、
所定の周波数のマイクロ波を発生するマイクロ波発生器と、
前記マイクロ波発生器が発生するマイクロ波を前記スロットアンテナに導くマイクロ波導入路と、
処理ガス供給源から供給される処理ガスを前記処理容器に導入する処理ガス導入手段と、
前記処理容器内に導入された処理ガスを、前記載置台に載置された基板の上面より下方の排気口から排気する排気手段と、
請求項1ないし11のいずれかに記載のエッチング方法を実行する制御部と、を備えることを特徴とするエッチング装置。 - 半導体装置の製造方法において、
素子、及び素子分離膜によって分離されてなるPMOS領域及びNMOS領域を有する半導体基板を準備する工程と、
前記素子、PMOS領域及びNMOS領域を覆うように窒化シリコン膜を形成し、前記窒化シリコン膜の上に積層された酸化シリコン膜である絶縁膜を形成する工程と、
請求項1ないし11のいずれか1項に記載のエッチング方法により前記絶縁膜をエッチングする工程と、
を備える半導体装置の製造方法。
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US9614053B2 (en) | 2013-12-05 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacers with rectangular profile and methods of forming the same |
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