TW200540976A - Method of controlling trimming of a gate electrode structure - Google Patents

Abstract

A method and processing tool are provided for controlling trimming of a gate electrode structure containing a gate electrode layer with a first dimension by determining the first dimension of the gate electrode structure, choosing a target trimmed dimension, feeding forward the first dimension and the target trimmed dimension to a process model to create a set of process parameters, performing a trimming process on the gate electrode structure, including controlling the set of process parameter, trimming the gate electrode structure, and measuring a trimmed dimension of the gate electrode structure. The trimming process may be repeated at least once until the target trimmed dimension is obtained, where the trimmed dimension may be fed backward to the process model to create a new set of process parameters.

Description

200540976 IX. Description of the invention: [Technical field to which the invention belongs] Cross-references of related patents The present invention relates to US Patent Application No. 10 / 756J59 (No. 071469-0307410) filed on January 4, 2004 ), And take it all into the examination materials and in this manual. ^ Field of Invention The present invention relates to semiconductor manufacturing, and in particular, to a method for controlling the trimming of an imperial structure in a chemical trimming process. A package

[Prior technology] Electrical systems are used in the manufacture and processing of semiconductors, integrated circuits, displays, and other devices or materials. Plasma processing can be used to transfer the lithographic mask of the integrated circuit to the semiconductor substrate. The lithographic mask may include an etch-resistant photoresist layer deposited on the substrate, exposed to a selected lithographic pattern, and developed. In addition to photoresistive acoustic lithographic masking structures, other masking layers may be included, such as anti-reflection coatings (lRci a: ^ flective coatings). The ARC layer is commonly used to reduce light reflection 'from the substrate during the lithography step, and a sacrificial mask can be used to pattern the area on the substrate. Jing Wu butterfly, shooting look at the _ system fixed body ί ΐ ΐ set f minimum feature size is close to the deep sub-micron type, in order to meet the requirements of more Si Λ and digital circuits. The key dimensions of the circuit (CD, device editor ==== patterned photoresist for the photoresist manufactured). The layer size exceeds the positivity > positive patterned photoresist (PR, limit. During plasma side process). (^: 5, 200540976 of the lithography technique of the money-engraving method) When the physical parameters (such as focus and exposure) are fixed, the dense (intermediate CD secret value, this fairy is the towel ^) of the isotropic rhyme carving process [Content of the invention] Process parameter adjustment process, including controlling the size of the A domain in the trimming process to control the size of the A field, the board is loaded with :, Jiir multi-gate electrode structure. The processing tool contains -base- Biography; i == ί = of the substrate, Ξ's = can be trimmed by the first dimension and target G; ϊ ϊ system, used to measure the first system of the closed electrode structure [implementation] examples Nozaki's entire gate electrode structure is used to trim the gate technology; by chemically smaller than the size of the photolithography, or it can be == 1. The size after trimming can be shown in Figure 1A, which contains the substrate 100, and high dielectric organic The arc layer touches and patterned photoresist layer. The UIM and the layer 104 may be a stone-containing layer, such as an amorphous stone layer. Poly 3 1 0. Gate electrode Alternatively, the gate electrode layer 104 may be a metal-containing layer, such as Group 3, which belongs to 200540976, metal nitride (such as TaSiN, ™), or metal lice (such as ru〇2 ) Or arbitrarily handle 4 people ?; Rib 2, HfSi〇x, Zr (v or z7rSiom) ^ several layers can be moved, for example, containing a mask to warm up the sound of the photoresistor, χ or a combination of them. The patterned layer 10 is formed by transmission. In the unexposed area, a patterned photoresist layer can be used. It has an initial lithographic size of 122 NF3 or two or more of them. 4 6 2 6 Or; 〇 Zhong Zhonggang 'organic vertical layer 106, and the extremely small value of the difficult layer 104 ^ ^ ω ω ΐϋ before the whole process can be performed, the photoresist layer 108 and organic arc II 108 ^ t in the picture, or, Photoresist can be used during the trimming process ^ In FIG. 1C, the gate electrode layer 104 is characterized by a first horizontal ruler and a vertical dimension 122. The chemical trimming process can further reduce CD (sixth horizontal dimension 6 ', FIG. 1D) It is smaller than the lithographic size of 120, without changing the D-offset or contour of the gate electrode layer 104, and there may be very few changes on the wheel hub. In the process, the inter-electrode structure 10 in FIG. 1c may be exposed to a reactant gas that reacts isotropically with the electrode structure 10 to form the reverse = H〇4b shown in FIG. 1D. In a heat treatment or an electric process In this case, the reactant gas may be exposed to the idler structure, and the thickness of the reaction layer 104b depends on the processing conditions, such as the species of the reactant gas, the pressure of the reactant gas, the exposure time, and the temperature of the substrate. The shape of 〇4b is to hinder the further reaction between the gate electrode layer 10 and the reactants by acting as a physical diffusion barrier. The gate electrode structure 10 is exposed to the reactant gas for a period of time to form a reaction layer 104b having a desired thickness. 200540976, 2 schematically shows the thickness of the reaction layer as a function of the% of reactant gas exposure according to one embodiment of the present invention; the curve 200'-22 'shows that for different processing conditions, the reaction = thickness is as shown in Figure 2. Indication '-At first, you can see that the thickness of the reaction layer is fast, plus: after that, the exposure time increases, and the rate of increase is "gradual." The "smoothing" is due to a self-limiting reaction, in which the thickness of the reaction layer approaches-a progressive value. In fact, the σ person selects the process conditions of the reaction layer that can have the required control and repeatability on the time scale (fine) that is generally feasible for semi-body manufacturing. Therefore, the thickness of the layer and the allowable Different dressing recipes with good reproducible control of the dressing process.时 门 ίίίίΓΪΐί As far as practical manufacturing of semiconductor devices is possible, t = and about 3G seconds), we can process the strips according to the prototyping process. There is a thickness of _ η half- Chiang, layer reaction between about 2 nm and about 5 nm. A S02 reaction layer was formed. • The plate was used to stimulate oxygen species. If the processing system needs to be removed from the substrate in the future, the 02 plasma source can be a remote plasma source. In one embodiment, an oxygen-containing gas such as O 2 or O 2 may be used to form the gate electrode to form a SiO 2 reaction layer. In the present invention, a Weihua process is used. The oxidation process can, for example, immerse the substrate in warm water or acid value to select the electropolymerization processing conditions and the substrate temperature, so as to generate about _Thickness of the thickness of the reaction layer of If 3 2 reaction layer will appear at room temperature after about 15 seconds. And, longer exposure will cause the thickness of the reaction layer to increase. The short processing time required to form the SWA layer has resulted in the required high substrate production level to form a reaction layer with a sensitive thickness i04b ′ 1 ΐ ϊΐ Structure 1G exposed to the reactant gas. After that, the anti-static 104b is removed (stripped) from the unreacted gate electrode layer. For example, the reactive layer 104b can be removed by exposing the gate electrode structure 200540976 to an etching gas. The choice of an etching gas capable of removing the reaction layer 104 may depend on the material of the gate electrode. The removal of the reaction layer 104b is selective to the unreacted gate electrode material and results in trimming the gate electrode layer 104a as shown in FIG. 1E. For example, the etching gas may be an aqueous solution vapor (HF㈣). As those skilled in the art will know, HF (R) has a higher selectivity for SiO2 than Si, which allows the rapid and selective removal of the SiO2 reaction layer 104b from the remaining Si gate electrode layer 104a. The exposure of the Si02 reaction layer 104b to the HF-silver etching gas can be performed for a predetermined period of time sufficient to complete the removal of the Si02 reaction layer 104b. In an example of the present invention, the 4 nm-thick Si02 reaction layer 104b can be removed in about 10 seconds. The trim gate electrode layer 104a is characterized by a first horizontal dimension 118 and a second vertical dimension 124, which are smaller than the first horizontal dimension 120 and the first vertical dimension 122 in FIG. IC, respectively. If you want to further trim the gate electrode layer 10 乜, you can repeat the trimming process. Repeat the trimming process to form the reaction layer 104d in FIG. 1F and the trimming gate electrode layer 104c with the new sizes 116 and 126 in FIG. 1G. Another example of trimming and removing the oxide film 104a is the use of chemical oxide removal (COR, cmde removal), using the last gas and Li 3 to react with the oxide film, and then using heat treatment to evaporate the trimmed product; another C () R example is the use of remotely polymerized and NH3 engraved gas; another example of CO is the use of nh4f subtraction to thermally react with subtractive film. Trim to remove oxide film inspection-use wet process. For example, a wet process can immerse a substrate in a buffer solution. ..... f The entire cycle includes forming a reaction layer and removing the reaction layer. In the case of lc_m, the second horizontal dimension of the inter-electrode layer 104 is reduced to 12G, which is twice as large as the rule ======. In the example, the first horizontal dimension of the inter-electrode layer can be reduced to 120 °. Coincident size is about 4nm. In the example, the inch may be 120nm and the first vertical dimension 122 may be about 14 °: the trimming process with a number of trimming cycles may reduce the first horizontal dimension of 1240nm and reduce the first vertical dimension of 122 to about i 〇〇nm. , Force intention. In FIG. 3A, 'the metal-containing layer 103 is inserted] between the electrode layer 104 and the dielectric layer 102. For example, one metal-containing layer 200540976, or RU〇2 material or any combination thereof. For example, a high dielectric constant ^ HfSi0x ^ Zr〇2 ^ more arbitrary combination. Trimming the gate electrode layer 104 may be performed as described above in FIGS. 1B-1G to form a gate electrode junction having dimensions 116 and 126 as shown in FIG. 3B.

From Γ, the modified electrode layer 1G4e can be used as a mask layer in the anisotropic etching process to define a sub-lithographic etching feature in the metal-containing layer 103, as shown in FIG. 3C. According to the etching ratio of these layers, the etching of the metal-containing layer 103 reduces the size 126 of the gate electrode layer 104c. In the example of the polysilicon layer 104 and the TiN layer 103, the side ratio may be about L5 (wondership). Therefore, in order to achieve the desired vertical size of 128, the size of 126 may be selected according to the etching ratio of the layers 104 and 103. Using halogen-based gases (such as chlorine), TaN, TiN, and dipping materials can be electrocuted. For example, a mixture of oxygen and chlorine gas can be used to perform plasma etching on chemical readings. Alternatively, as shown in Figs. 4A-4B, an inorganic ARC layer may be used to avoid reducing the size 126 while engraving the metal-containing layer 103. 4A-4B are schematic cross-sectional views of a processing flow for trimming a gate electrode structure according to still another embodiment of the present invention. The gate electrode structure 10 in FIG. 4A includes a gate electrode layer 104-a trimmed inorganic arc layer 106 to form the trimmed gate electrode structure 10 in FIG. 4B. For example, the inorganic ARC layer 106 may contain SiN, and the dielectric stone 102 may be selected from SiO2, SiOxNy, or a high dielectric constant material such as Hf02, HfSi0: Zr02, or ZrSiOx. x:-By exposing the gate electrode structure 10 to stimulated oxygen species in the 02 plasma, the SiNARC layer 106 and the polysilicon gate electrode layer 104 can be trimmed. The growth rate of the reaction layer on the siNARC layer and the polysilicon gate electrode layer can be changed, but the progressive reaction layer thickness on the polysilicon material is expected to be smaller. 5A-5D are schematic cross-sectional views of a processing flow for trimming a gate electrode junction according to yet another embodiment of the present invention. The gate electrode structure 10 includes a substrate 100, a dielectric layer 102, a gate electrode layer 104, an inorganic ARC layer 106, and a patterned photoresist layer 108. For example, the inorganic ARC layer 106 may contain SiN, and the dielectric layer 102 may be selected from ⑽2, SiOxNy, and high dielectric constant materials such as Hf〇2, HfSiox, Zr〇2, and 200540976. FIG. 5A shows The inorganic ARC layer 106 is etched by a slurry and a part of the gate electrode is etched. Figure 5B: The power of a journey is low and you are low— &# μ a

ZrSiOx. The gate electrode structure after the etching of the inorganic ARC layer 1 (> 6 and part of the gate electrode layer 104 after etching the gate electrode structure 104. Fig. 5B shows the gate electrode structure 10 after a trimming cycle, and Fig. 5C The gate electrode structure 10 is trimmed after two trimming cycles, and FIG. 5D shows the gate electrode structure 10 after the anisotropic etching of the gate electrode layer 104c. FIG. 6 is a schematic diagram of a gate electrode structure 10 according to an embodiment of the present invention. The production map of the gate electrode structure is trimmed. At 600, the manufacturing process begins. At 610, the gate electrode structure including the first dimension ^ is set in the processing system. At 62, select a trimming ^ Optional-a kind of energy can be used for the gate The health of the electrode structure is as follows: ^ The electrode structure reacts to form a reaction layer. In the present invention, ―Second = Huntable by Lai processing or Plasma processing, the gate electrode is exposed ^, so it has less than the first- In the second embodiment of the size-removing crystal, the reaction layer can be removed by exposing the reaction layer to a reverse etching gas. The remaining part of the hybrid reaction layer is an embodiment of the present invention. In order to provide a method of trimming the one-pole structure, the process die g: type is used to control the gate. Mathematical function to inverse process parameters. The process model can use t = f (x) + b ⑴, ⑴ 甲 所: where t is the thickness of the reaction layer, b is the pitch, and the process is the process parameter group. For example, the function The system is used to repair the power and processing time. The relationship between the body pressure, substrate temperature, and thickness is referred to as the process parameters of the n 4 () towel and other process parameters of the reaction layer. 2 Contains single-variable process parameters and a 200540976 tg (p) + c (2) physical gas pressure, c is a constant. The relationship between the pressure of the processing gas and the reaction is called the pressure-based trimming curve.… Or ^ 'By changing at least one additional process parameter, (such as the power of electricity), to the -Qianken force trimming curve. Limitations on a group of available pressure trimming operating conditions, such as pressure control limits: limit, gas Resolution of flow controller. By re-trimming the process with κ Μ and making different process parameters available, you can create a process with 修 trimming curve group: Ξ thickness. You can use the process model to control the process parameter group, such as As shown in equation (3): 'X = f1㈣ (3) where f is an inverse function of f. ^ In one embodiment, the first dimension of the gate electrode structure is inch CDq (as in size 120 in FIG. 1C), and the target trimming dimension is the key dimension CDt. (As in the dimension m in FIG. 1E or in the figure ig = 2 meshes. Ϊ́ 前 feed forward the size CD0 & CDt to the controller used to according to the equation: 10 times the target reaction layer thickness:) t = (CD〇 一 CDt) / 2 (4) In the example of using the process gas as the single-variable inch CD0 and the target trimmed size CDt substrate, the processing required to obtain the target trimmed size CDt is calculated by a ruler. Gas Lili ρ: formula () can be p 2 g-1 ((CD〇—CDt) / 2 — c) ⑺ center = the thickness minus the thickness of the reaction layer is greater than the value achieved in the single-knowledge, May require multiple trimmings

The trimming process is re-trimmed to produce the same reaction layer thickness or different reaction layers, and the thickness is larger. Figure 7 is a flow chart for controlling according to an embodiment of the present invention. At 762, the process begins. At 764, in the first dimension of the electrode structure trimmed by DJ :: J; enter the first dimension and step, the positive dimension of the dimension V into the process mold 12 200540976 ί 2 3 dimensions and the target trim size to create a Process parameter group. Measure the trim size in steps. If the trimming process 768 produces a trimming ruler larger than the desired target trimming size, the process 768 is repeated at least once until the target trimming size is obtained. This can include feeding the trimming ruler to the process surface 766, and setting up a new process. Repeat the trimming process until the target trimming ruler is obtained. A new process parameter group can be established before each trimming process. When the trim size is obtained, the process ends at 768. Fig. 1 shows a method for trimming an electrode junction according to an embodiment of the present invention. The tool _ can be, for example, Tokyo Electron Limited, Akasaka, Japan, Akasaka, Japan. ) U_Me money carving tool. The processing tool_ includes a substrate loading chamber 8i0 and Na, a processing soil 83 ^ 860, an automatic transfer system 87o, and a controller_. = Plasma money of photoresist layer 108, ARC layer 106, and inter-electrode layer (as shown in the second push >. ^ 二] i〇3i · as shown in Figure 3) can be carved in the processing system 840 in two consecutive In the embodiment, by exposing the gate electrode structure to the reaction, it can be performed in the system: and by exposing the gate electrode to the side, the reaction layer can be removed in a row. ^ In addition and removal can be in the single-processing system as described above or repair cycle can help profit. High background pressure containing humic gas reactants It continuously reacts with the gate electrode layer and can corrode the semiconductor substrate. ° In the embodiment of the present invention, an analysis chamber that processes the structure size of the electrode can be used. According to the measured size, another trimming prescription can be used to perform another trimming cycle or stop the trimming process. The Department of Science and Technology m 13 200540976 can be, for example, from TIMBRE TephnnWY. Position profilometer (odptm) or women (clara, CA). Optical number v drag electron microscope (SEM).

The processing tool 80 () may be controlled by the controller 880. The system is equipped with 880 A plate loading chambers 810 and 820, and the processing system can be connected to the basic system, including the system _860, and the automatic transfer system 870. Γ, the process stored in the memory of the controller 880 controls the aforementioned components of the processing tool according to the process desired by f, and any function. In addition, the controller 88G can be used to establish. ,: Crying, _Λ The process model of the entire process is stored in the processing tool_

Austin% 〇 °, λα are only examples of DELL PRECISI0N WORKSTATION 610 'which can be squatted from Dell Corporation (D1, as), or' i Administrative Tools _ may include-control 11 above the rack to perform the above functions' ποΛΙΐΙ The computer system 120 in the embodiment of the present invention is set up, and the computer system 1 \ work control 11 ′ may be used to perform any or all of the above functions. The computer system 1201 includes a bus or other transmission mechanism for transmitting information, and a processor 1203 connected to the bus 1202 to process information. = System 1201 also includes main memory 1204, such as random access memory (RAM) or other dynamic storage devices (such as DRAM, dynamic RAM), connected to the bus 1202. , Static RAM (SRAM, static RAM), and synchronous DRAM (SDRAM, synchronous DRAM)) to store data and instructions to be executed by the processor 1203. In addition, the main memory 1204 can store temporary variables or other intermediate information during the execution of instructions by the processor 1203. The computer system 1201 further includes a read-only memory 1205 connected to the bus 1202 or other static storage devices (such as a programmable ROM (PROM, programmable ROM), erasable PROM). (EPROM, erasable PROM), 'and PROM (EEPROM, electrically erasable PROM)) to store static information and instructions of the processor 1203. The computer system 1201 also includes a disk controller 1206 connected to the bus 1202 to control one or more storage devices such as a magnetic hard disk 1207 and a removable media drive 1208 (such as a floppy disk drive) to store information and instructions. Drives, read-only discs 14 200540976 drives, read / write drives, drive cabinets, tape drives, and removable magneto-optical drives). Use appropriate device interface (such as small computer system interface (SCSI), integrated device electronics (ide, integrated device electronics), direct memory access (DMA, direct memory access), or super-DMA) A storage device can be attached to the computer system 1201.

The computer system 1201 may also include special-purpose logic devices (such as application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), and field-effect programmable gate array FPGAs, Field Programmable Gate Arrays)). The computer system can also include one or more digital signal processors (DSPs, digital signal processors) such as TMS320 series from Texas Instruments, DSP56000, DSP56100, DSP56300, DSP56600, and DSP96000 series chips from Motorola, DSP1600 and Lucent Technologies DSP3200 series or ADSP2100 and ADSP21000 series from Analog Devices. Other processors specifically designed to handle analog signals that have been transformed into digital domains can also be used. The computer system may also include one or more digital signal processors (DSPs, digital signal processors) such as TMS320 series from Texas Instruments, DSP56000, DSP56100, DSP56300, DSP56600, and DSP96000 series chips from Motorola, DSP1600 and DSP3200 series or ADSP2100 and ADSP21000 series from Analog Devices. Other processors specifically designed to handle analog signals that have been transformed into digital domains can also be used. The computer system may also include a display controller 1209 connected to the bus 1202 to control a display for displaying information to a computer user, such as a CRT cathode ray tube. The computer system includes an input device, such as a keyboard and a display device 1212, to interact with the computer user and provide an office. For example, the pointing device 1212 may be used to transmit directions, information processing benefits 1203, and to control surface display. The mouse moved by the cursor on the device 121 and the track ϋΛΙ pointing stick. In addition, the printer may provide a list of print data stored and / or generated by the computer system 1201. 15 200540976 Contains steps to execute the instructions contained in _ at the ^ device to execute the body contained in main memory. Therefore, the embodiment is not limited to any specific hardware circuit and software. 2.1 includes at least " " computer-readable ship or memory, and other information described in this article. Computer-readable media (t = PROM), D can, squ, (, physical media, carrier wave (described below), or any of the tenth invention includes a combination stored in any or computer-readable female body The use of the above = f system 12 G1, the driving device or the implementation of the & type printing and printing production personnel of the present invention) interactive software electric two = (but not limited to) device, converter, operating system, development of this computer readable ship It also includes all or part of the computer code device of the computer program of the present invention that is processed (if the processing is decentralized), which can be any decoding (in this type of agency 'including but not limited to handwriting (like Code programs, kinetic energy = DLLs (dynamic link libraries), Java programs (Java core I ·), two completely executable programs. In addition, some of the inventions can be processed in order to obtain Better performance, reliability, and / or cost. Anyone can rely on "electricity · reading miscellaneous" for any kind of media and providing instructions to process 1203. Computer-readable media can take many forms, including 16 200540976 Independent media, ephemeral media, and dumping ship. The body includes, for example, a hard disk, a magnetic disk, and a magneto-optical disk, such as a hard disk 1207 or a demagnetized = intentional f, such as the main memory 1204. It is transmitted to a certain body package 3, and it is a wire of the exchange machine row 1202 The order of the coaxial cable is ίίϊίίίΐ The 2-terminal computer can be used to execute all of the "copy of this account" in the distance, and send it through the infrared line of the modem to send Z-infrared ^ to convert the data into Infrared signal. Connected bus = Infrared L can be received and carried on the infrared signal. Carry information with the main 1202 to the main memory ^ = Retrieve and execute the command with 12G4. The main memory or 1112G3 will execute the status report or read it The storage computer system 1201 also includes a communication interface 1213 connected to the bus 1202. it! Surface = 1 is used for two-way data communication to the network connection 1214, which is connected to, for example, a local area Network (LAN, local area) (_215 or another-communication network 1216 (such as the Internet) is connected, the communication interface 1213 can be a scale interface connected to any packet-switched LAN as another-example 'communication interface 1213 can be Asymmetrical digital subscriber line r line) card, integrated service digital network (isdis 0 card, modem) to provide the best-in-class bribery type: secret communication link can be used to implement wireless links, and send it on any device, rail interface 1213 and Receive electrical, electromagnetic, or optical signals that carry digital data streams representing different types of information. Network link 1214 typically provides data communication via-or multiple networks. Other data devices. For example, network link 1214 may be via local network 1215 (Such as lan) '17 200540976 or ,,,, two by serving the force kt, (which comes through the communication network 1216

Connection to another -β 4 W 锢 玖 it month. For example, the local network 1215 and communication 3 layer (such as CAT 5 Wei, coaxial _, fiber, etc.). "Different networks ^ On the network link 1 call and communicate with the Jian Cui 1 bit through the communication interface to the computer system 121G) Can be described by the baseband signal or the carrier ^ as two, No. 1 = two baseband signals to describe Digital data is transmitted in the unmodulated electrical pulse form of the digital bit stream, which is broadly interpreted as a symbol, and each symbol can be transmitted using at least digital data to modulate the carrier, such as through transmission. : "1st leather transmission, breadth, prostitute_switch keying, sftitt keyed) 仏 5 tiger. Therefore, the consultation office _ ^ r, mining, ^", one husband, one of them, and the digital department can pass "Wired" communication channel instead of a predetermined frequency band l? N, ㈣ "= and 16, network key 1214, and communication ^, network key ΐΙΐΓ can: rf01 can send and receive data (including code ). The connection between this personal digital assistant (PDA), laptop minebrain power suit 217 (taxi m 士 9m phone or mobile phone). Monthly subscription, charge 1201 can be used to implement the present invention

Structurally perform trimming and manufacturing of decorative materials * Called by the gate electrode group L-system 1201 Anmengyang 1 set. According to the present invention, it is possible to establish a computer system, a computer model, and a process model and control the production process of the women's clothing, and control the various kinds of money and changes in the present invention. Therefore, it should be understood that it is implemented in other manners clearly stated in the attached patent application. $ '柄 明 can be simply explained as shown here.] Figure 1A-1G shows a schematic cross-section of the processing flow according to one of the present invention. Figure 2 schematically shows the structure of the trimmed gate electrode. Mao Yue 5 knows the thickness of the reaction layer with the reactant gas exposure as a function of 18 200540976; Figures 3A-3C show a schematic cross-sectional view of another process according to the present invention; Figure 4A is used to modify the structure of the gate electrode -4B shows a schematic cross-sectional view of a processing wire according to another embodiment of the present invention; θ & for example, for trimming an electrode junction. Figs. 5A-5D show a schematic cross-sectional view of another processing process according to the present invention. , The flow of trimming the pole structure with the ribs of the township gate—the ribs of the embodiment, the procedure ^ handles the tool of one embodiment to control the repair of the idle electrode structure according to this implementation Trimming the pole structure. Fig. 9 is an illustration of a computer that can execute the present invention. Description of component symbols: 10 ~ gate electrode structure 100 ~ substrate 102 ~ high dielectric constant layer 103 ~ metal layer 104 ~ gate electrode layer 104a ~ gate electrode layer 104b ~ reaction layer 104c ~ repair gate electrode layer 104d ~ Reaction layer 106 to organic ARC layer 108 to patterned photoresist layers 116 and 126 to new size 118 to second horizontal size 120 to first horizontal size 19 200540976 122 to initial lithographic size (Figure IA) 122 to first Vertical size (Figure 1C) 124 to second vertical size 128 to desired vertical size 800 to processing tools 810 and 820 to substrate loading chamber 830 to 860 to processing system 870 to automatic transfer system 880 to controller 1201 to computer system 1202 ~ bus 1203 ~ processor 1204 ~ main memory 1205 ~ read-only memory 1206 ~ disk controller 1207 ~ hard disk 1208 ~ removable media drive 1209 ~ display controller 1210 ~ monitor 1211 ~ Keyboard_ 1-212 ~ pointing device 1213 ~ communication interface 1214 ~ network link 1215 ~ local network 1216 ~ communication network 1217 ~ mobile device 20

Claims (1)

200540976 X. Scope of patent application: 1. A method for manufacturing a semiconductor device, including: determining a first size of a gate electrode structure; selecting a target trimming size; The Heidi dimension and the target trimming size are feed forward to a borrowing and one process parameter group; and a clothing pull type to build a trimming process on the gate electrode structure, including ... controlling the process parameters in the trimming process Group, and trim the gate electrode structure. 2. If the semiconductor device according to item 15 of the patent application is applied, one of the trimmed gate electrode structures is trimmed. Fang Qu, including measurement 3. If the method of manufacturing a semiconductor device in the scope of the patent application No. 2 process, at least-times' until the target trimming rule ^ 3 heavy m system, the third half-frequency device Manufacturing method, wherein the repairing pain trimming size is established to the process model to create a new manufacturing process, wherein the manufacturing process is calculated from a combination of the first size, the trimming size, and the target trimming more The thickness of the reaction layer; and one, one, or _ based on the thickness of the reaction layer to determine the process parameter set. 6 Fenru's method of manufacturing a semiconductor device under the scope of patent application No. 5, the decision of J array includes selecting at least process parameters while maintaining its process parameters. The system includes processing gas pressure, substrate temperature, plasma power, money processing time, or a combination of two or more of them. 8. The manufacturing method of the material device according to item 2 of the scope of patent application, wherein the measurement includes the use of scattering technology, scanning electron microscope (SEM), or both to determine 21 200540976 Rong Yi one size 9 packs $ patent application The method for manufacturing a semiconductor device according to item 1, wherein the reaction of the trimming electrode structure forms a reaction layer; and the reaction ^ selectively removes unreacted portions of the idle electrical connection structure. The scale class of the scale of the Yuandi tomb was formed in a self-limiting process. ¥ The method of manufacturing a body garment, wherein the reaction 11. The ninth car top of the patent application scope includes a manufacturing method of heat treatment, plasma treatment, or de-dressing, wherein the formation gas. Either or both 'expose the free electrode structure to the reaction 12. The strong reactant gas as described in item 丨 丨 of the patent application range includes stimulated oxygen-containing gas. The manufacturing method of Douyizhi, wherein the anti-13. The semiconductor development department of the seventh aspect of the patent application scope includes the manufacturing method of the exposed electrode structure, wherein the formation 14. The selective removal includes a manufacturing method of the gate electrode structure, wherein the selective removal includes the manufacturing method of the gate electrode structure, wherein the option 16. The semi-portable removal of The gate electrode structure is manufactured by Fang Yan, where the selection is made by heat treatment. . HF and _ oxygen body, and then exposed 17. If the semi-conductive removal of item 9 of the scope of patent application includes fabricating the gate electrode structure, the selected body is then exposed to heat treatment . *; Plasma NF3 and NH3 gas 18. The method of removing the gate electrode structure according to item 9 of the scope of the patent application includes the manufacturing method of the gate electrode structure, among which the option 19. The process of the scope of the patent application, item 9. And the removal is implemented in a single processing system, a manufacturing method in which the formation and removal are performed in a multiple processing system. ~ The method of manufacturing a semiconductor device according to item 9, wherein the method of manufacturing a semiconductor device according to item 9, wherein the formation is to form an oxide layer on the surface of the "Hieran" electrode. The method of manufacturing a semiconductor device according to claim 1, wherein the inter-electrode structure includes a gate electrode layer. / Ding Bi, the method of manufacturing a semiconductor device according to item 23, wherein the idle electrode layer has a stone-containing layer, a metal-containing layer, or both. For the manufacturing method of semiconductor money, please refer to item 24. The manufacturing method includes the non-, or =, 247Λ ^ Λ manufacturing method, where the intermetallic oxide, or i = = 3 = f: Metal, metal vapor, and metal 2 belong to 7ΐ: == The method of manufacturing the semiconductive Zhao device of item 26, which directly contains the whole, brain N, Ru, or Ru02 or two of them U; 28 · Semiconductor _ Mengwei pole structure, such as the scope of application for patent, includes ARC layer. A method for fabricating a body garment, wherein the gate 29. The semi-conductive Xu Meng layer such as the 28th in the scope of patent application includes an organic ARC layer or an inorganic arc layer. ", clothing & method, wherein the transfer layer of the ARC 30 · 28 item includes SiN. We show the method, in which the ARC 31 · as the semi-conductor of the patent application scope No. 1 repair the gate electrode structure as a fresh layer method, but also includes the use of 32 ·-computer-readable media, including useful H-direction _ ° When the program instruction is a program instruction executed on a processor, the processing tool executes step 1 of the scope of patent application 23 200540976. 33 · —A semiconductor device, including the gate electrode structure of the repair method, which is provided by the method of the first side of the special machine 34.—A processing tool, including: The first electrode structure t with the _th dimension is used to transfer the substrate in the processing tool; a trimming process is performed on the electrode structure by trimming the i-inch ribs, which can be built by the first dimension And the target trimming size Σ arrayΐϊ process model, and the trimming rule ^ or = line 'rib' rhyme gate electrode structure that is controlled in the trimming process, the -dimension of the rhyme gate electrode structure, and 34 items of treatment sanitation equipment , Its towel should be at least-treatment system ^. i The clothing process is executed at least once until the target trimming ruler is measured for 3 items of fiber and 35 items. The other-the processing system measures and returns the secret size to the at least one controller to establish-new 37. If you apply for a patent In the 34th item of the scope of science and technology, the -size, the trim size, and the target trim include at least one of the reaction layer thicknesses; and the wood chip determines the process parameter group based on the reaction layer thickness. = · If the processing tool of the scope of patent application No. 37, wherein the at least _ controller is to determine the system by selecting at least one process parameter while keeping other process parameters fixed. 39. The processing tool according to item 34 of the patent application scope, wherein the process parameter set includes processing gas pressure, substrate temperature, plasma power, processing time, or a combination of two or more of them. & 40. The processing tool of claim 34, wherein the other processing system includes scattering technology, a scanning electron microscope (SEM), or both. 41. The processing tool according to item 34 of the application, wherein the at least one processing system: forms a reaction layer by reacting with the gate electrode structure; and uses chemical etching to selectively remove unreacted portions of the gate electrode structure The reaction layer was removed in portions. The processing tool according to 41, wherein the reaction layer is formed at 43. The processing tool according to item 41 of the application, wherein the at least one processing system 1 exposes the gate electrode structure to a reactant gas in a process, a process, an electropolymerization process, or both to form the reaction layer. 44. The processing tool according to item 43 of the application, wherein the reactant gas comprises a stimulated oxygen-containing gas. 45. The processing tool of item 41 in the patent scope, wherein the at least one processing system = the gate electrode structure is exposed to a wet oxidation process to form the reaction layer. Second, the processing tool of claim 41 in the patent scope, wherein the at least one processing system is exposed to a gas engraved to remove the reaction layer. For example, the processing tool of claim 41 in the patent scope, wherein the at least one processing system is exposed to the HF electrode to remove the reaction layer. _ The processing tool according to item 41 of Shenyan's patent, wherein the inter-electrode structure of the at least one processing system is exposed to HF and Nh3 gas, and then to heat treatment. Exposing the processing tool of item 41 in the scope of patent application 'wherein the at least one processing system = the free electrode structure is exposed to NF3 and Nil · in the remote plasma, and then exposed to heat as described in item 41 of the scope of patent application A processing tool, wherein the at least one processing system exposes the gate electrode structure to a wet process. 51. The processing tool of claim 41 in the scope of patent application, wherein the at least one processing system 25 200540976 is composed of a single processing system. The treatment of item 41 in the middle patent scope includes multiple processing systems. The at least one processing system, such as ,,,, etc. 53. Such as the application of the scope of the patent, the size and size. The size of this brother is lithography 54. If the processing tool on the first page of the scope of the patent application is applied, the application of Shenxing Yuhuan will be converted to the processing tool of the system in the electrode layer r patent scope of item 34, where the The gate electrode structure includes the i6. If the application includes a processing device, the Shelangchi layer contains the processing tool of item 56 in the range containing Shixi, where the gate electrode layer contains Shixi including amorphous stone, polychop, or SiGe, or two or two of them. For example, claim 56. The processing tool ’wherein the gate electrode layer includes a metal containing metal ^ ί ^ _ contains a metal compound, a metal oxide, or a combination of two or more of them. I, τ = The processing tool according to item 58 of the patent scope, wherein the metal-containing layer includes a, iN, TaSiN, Ru, or Ru02, or a combination of two or more thereof. 60. The processing tool of claim 55, wherein the gate electrode structure further includes an ARC layer. 61. The processing tool according to claim 60, wherein the ARC layer includes an organic ARC layer or an inorganic ARC layer. 62. The method for manufacturing a semiconductor device according to claim 60, wherein the ARC layer includes SiN. 63. The processing tool of claim 34, wherein the at least one processing system is installed for a wet process. 64. The processing tool according to item 34 of the patent application scope further includes an additional processing system installed for plasma etching. 26 200540976 65. The processing tool of claim 64, wherein the additional processing system is installed for RIE. Eleven schemes: 27