JP2007528123A - 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 - Google Patents

高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 Download PDF

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Publication number
JP2007528123A
JP2007528123A JP2006537994A JP2006537994A JP2007528123A JP 2007528123 A JP2007528123 A JP 2007528123A JP 2006537994 A JP2006537994 A JP 2006537994A JP 2006537994 A JP2006537994 A JP 2006537994A JP 2007528123 A JP2007528123 A JP 2007528123A
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semiconductor
region
regions
epitaxial growth
semiconductor region
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Japanese (ja)
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JP2007528123A5 (enExample
Inventor
ファン ベントゥム ラルフ
ルーニン スコット
カムラー トルシュテン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Priority claimed from DE10351008A external-priority patent/DE10351008B4/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007528123A publication Critical patent/JP2007528123A/ja
Publication of JP2007528123A5 publication Critical patent/JP2007528123A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2006537994A 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術 Pending JP2007528123A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10351008A DE10351008B4 (de) 2003-10-31 2003-10-31 Verfahren zur Herstellung von Transistoren mit erhöhten Drain- und Sourcegebieten mit unterschiedlicher Höhe sowie ein Halbleiterbauelement
US10/862,518 US7176110B2 (en) 2003-10-31 2004-06-07 Technique for forming transistors having raised drain and source regions with different heights
PCT/US2004/031038 WO2005045924A1 (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Publications (2)

Publication Number Publication Date
JP2007528123A true JP2007528123A (ja) 2007-10-04
JP2007528123A5 JP2007528123A5 (enExample) 2007-11-22

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JP2006537994A Pending JP2007528123A (ja) 2003-10-31 2004-09-17 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術

Country Status (4)

Country Link
JP (1) JP2007528123A (enExample)
KR (1) KR101130331B1 (enExample)
GB (1) GB2422488B (enExample)
WO (1) WO2005045924A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009500823A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
KR20230164472A (ko) 2022-05-25 2023-12-04 삼성전자주식회사 집적회로 소자

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124327A (ja) * 1998-10-14 2000-04-28 Toshiba Corp 半導体装置及びその製造方法
JP2002231908A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616582A (en) * 1898-12-27 Victor odqtjist and john c
US690636A (en) * 1900-12-19 1902-01-07 Joseph Coldwell Warp stop-motion for looms.
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
JP2964925B2 (ja) * 1994-10-12 1999-10-18 日本電気株式会社 相補型ｍｉｓ型ｆｅｔの製造方法
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
TW497120B (en) * 2000-03-06 2002-08-01 Toshiba Corp Transistor, semiconductor device and manufacturing method of semiconductor device
JP2002026313A (ja) * 2000-07-06 2002-01-25 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002043567A (ja) * 2000-07-27 2002-02-08 Mitsubishi Electric Corp 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124327A (ja) * 1998-10-14 2000-04-28 Toshiba Corp 半導体装置及びその製造方法
JP2002231908A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009500823A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法

Also Published As

Publication number Publication date
KR101130331B1 (ko) 2012-03-27
GB2422488A (en) 2006-07-26
WO2005045924A1 (en) 2005-05-19
KR20060108641A (ko) 2006-10-18
GB0607742D0 (en) 2006-05-31
GB2422488B (en) 2008-02-13

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