GB2422488A - An advanced technique for forming transistors having raised drain and source regions with different height - Google Patents

An advanced technique for forming transistors having raised drain and source regions with different height Download PDF

Info

Publication number
GB2422488A
GB2422488A GB0607742A GB0607742A GB2422488A GB 2422488 A GB2422488 A GB 2422488A GB 0607742 A GB0607742 A GB 0607742A GB 0607742 A GB0607742 A GB 0607742A GB 2422488 A GB2422488 A GB 2422488A
Authority
GB
United Kingdom
Prior art keywords
regions
different height
source regions
epitaxial growth
raised drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0607742A
Other versions
GB2422488B (en
GB0607742D0 (en
Inventor
Ralf Van Bentum
Scott Luning
Thorsten Kammler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10351008A external-priority patent/DE10351008B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0607742D0 publication Critical patent/GB0607742D0/en
Publication of GB2422488A publication Critical patent/GB2422488A/en
Application granted granted Critical
Publication of GB2422488B publication Critical patent/GB2422488B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Description

GB 2422488 A continuation (72) Inventor(s): Ralt Van Bentum Scott Luning
Thorsten Kammier (74) Agent and/or Address for Service: Brookes Batchellor LLP 102-1 08 Clerkenwell Road, LONDON, EC1M 55A, United Kingdom
GB0607742A 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height Expired - Fee Related GB2422488B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10351008A DE10351008B4 (en) 2003-10-31 2003-10-31 A method of fabricating transistors having elevated drain and source regions of different height and a semiconductor device
US10/862,518 US7176110B2 (en) 2003-10-31 2004-06-07 Technique for forming transistors having raised drain and source regions with different heights
PCT/US2004/031038 WO2005045924A1 (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Publications (3)

Publication Number Publication Date
GB0607742D0 GB0607742D0 (en) 2006-05-31
GB2422488A true GB2422488A (en) 2006-07-26
GB2422488B GB2422488B (en) 2008-02-13

Family

ID=34575412

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0607742A Expired - Fee Related GB2422488B (en) 2003-10-31 2004-09-17 An advanced technique for forming transistors having raised drain and source regions with different height

Country Status (4)

Country Link
JP (1) JP2007528123A (en)
KR (1) KR101130331B1 (en)
GB (1) GB2422488B (en)
WO (1) WO2005045924A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
DE102005030583B4 (en) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Method for producing contact insulation layers and silicide regions having different properties of a semiconductor device and semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US20020005553A1 (en) * 2000-07-06 2002-01-17 Fumio Ootsuka Semiconductor integrated circuit device and a method of manufacturing the same
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US20020106855A1 (en) * 2001-02-06 2002-08-08 Hidenori Sato Method of manufacturing semiconductor device
US20020158292A1 (en) * 2000-07-27 2002-10-31 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US616582A (en) * 1898-12-27 Victor odqtjist and john c
US690636A (en) * 1900-12-19 1902-01-07 Joseph Coldwell Warp stop-motion for looms.
JP2964925B2 (en) * 1994-10-12 1999-10-18 日本電気株式会社 Method of manufacturing complementary MIS type FET
JP2000124327A (en) * 1998-10-14 2000-04-28 Toshiba Corp Semiconductor device and manufacture thereof
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US20020008261A1 (en) * 2000-03-06 2002-01-24 Kabushiki Kaisha Toshiba Transistor, semiconductor device and manufacturing method of semiconductor device
US20020005553A1 (en) * 2000-07-06 2002-01-17 Fumio Ootsuka Semiconductor integrated circuit device and a method of manufacturing the same
US20020158292A1 (en) * 2000-07-27 2002-10-31 Mitsubishi Denki Kabushiki Kaisha Method of making field effect transistor
US20020106855A1 (en) * 2001-02-06 2002-08-08 Hidenori Sato Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
GB2422488B (en) 2008-02-13
KR20060108641A (en) 2006-10-18
KR101130331B1 (en) 2012-03-27
WO2005045924A1 (en) 2005-05-19
JP2007528123A (en) 2007-10-04
GB0607742D0 (en) 2006-05-31

Similar Documents

Publication Publication Date Title
TW200520106A (en) Technique for forming transistors having raised drain and source regions with different heights
TW200509391A (en) A device having multiple silicide types and a method for its fabrication
EP1598909A3 (en) Semiconductor device having quantum well structure, and method of forming the same
EP0989614A3 (en) TFT with an LDD structure and its manufacturing method
MX336500B (en) Insecticide for agricultural or horticultural use and method of use thereof.
ATE420376T1 (en) METHOD FOR ESTIMATING THE LOCATION OF A DEVICE
EP1873786A3 (en) Thin film semiconductor device and manufacturing method
TW200503076A (en) III-V compound semiconductor crystal and method for production thereof
EP2214198A3 (en) Isolated complementary MOS devices in EPI-less substrate
WO2004107406A3 (en) Semiconductor electronic devices and methods
WO2007056708A3 (en) A strain-compensated metastable compound base heterojunction bipolar transistor
TW200620539A (en) BiCMOS compatible JFET device and method of manufacturing same
EP0404464A3 (en) Manufacture of semiconductor devices
TW200635030A (en) Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide
WO2007025259A3 (en) MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
WO2006076991A3 (en) Method for producing a field-effect transistor, field-effect transistor and integrated circuit arrangement
TW200705712A (en) Method of producing nitride-based semiconductor device, and light-emitting device produced thereby
TW200631104A (en) In situ formed halo region in a transistor device
TW200515623A (en) Light-emitting device and method for manufacturing the same
TW200507080A (en) Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same
WO2007079372A3 (en) An oxygen enhanced metastable silicon germanium film layer
GB2422488A (en) An advanced technique for forming transistors having raised drain and source regions with different height
EP1182700A3 (en) Process for the selective manufacturing of a T-shaped gate
EP1113485A3 (en) Method for producing a semiconductor device
TW200514253A (en) Semiconductor component and method of manufacturing same

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20110917