JP2007525015A - 並列相補型FinFETの対を有する集積回路構造体及び該形成方法 - Google Patents
並列相補型FinFETの対を有する集積回路構造体及び該形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 230000000295 complement effect Effects 0.000 title claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 239000012212 insulator Substances 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 123
- 239000000463 material Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 14
- 239000007943 implant Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 6
- WFKWXMTUELFFGS-AHCXROLUSA-N tungsten-180 Chemical compound [180W] WFKWXMTUELFFGS-AHCXROLUSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
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Abstract
【解決手段】 相補的フィン型電界効果トランジスタ(FinFET)を用いる集積回路構造体のための方法および構造体を開示する。本発明は、第1フィン(100)を含む第1型FinFETと、第1フィン(100)に並列に延在する第2フィン(102)を含む第2型FinFETを含む。また、本発明は、第1型FinFETおよび第2型FinFETのソース/ドレイン領域(130)の間に配置される絶縁体フィンを含む。第1型FinFETと第2型FinFETとの間隔が1個のフィンの幅とほぼ等しくなるように、絶縁体フィンは、第1フィン(100)および第2フィン(102)とほぼ同じ寸法の幅にされる。また、本発明は、第1型FinFETおよび第2型FinFETのチャネル領域を覆うように形成された共通ゲート(106)を含む。ゲート(106)は、第1型FinFETに隣接する第1不純物ドーピング領域と、第2型FinFETに隣接する第2不純物ドーピング領域とを含む。第1不純物ドーピング領域と第2不純物ドーピング領域の差異が、ゲートに、第1型FinFETと第2型FinFETとの差異に関係した異なる仕事関数を与える。第1フィン(100)および第2フィン(102)はほぼ同じ幅である。
【選択図】 図1
Description
Claims (33)
- フィン型電界効果トランジスタ(FinFET)を用いる集積回路構造体であって、
第1フィンを有する第1FinFETと、
前記第1フィンに並列に延在する第2フィンを有する第2FinFETと、
前記第1FinFETおよび前記第2FinFETのソース/ドレイン領域の間に配置された絶縁体フィンと、
を含み、
前記絶縁体フィンは、前記第1FinFETと前記第2FinFETとの間隔が1個のフィンの幅とほぼ等しくなるように、前記第1フィンおよび前記第2フィンとほぼ同じ寸法の幅を有する、
集積回路構造体。 - 前記第1FinFETおよび前記第2FinFETのチャネル領域を覆うように形成された共通ゲートを更に含む、請求項1に記載の集積回路構造体。
- 前記共通ゲートが、前記第1FinFETに隣接する第1不純物ドーピング領域と、前記第2FinFETに隣接する第2不純物ドーピング領域とを含む、請求項2に記載の集積回路構造体。
- 前記第1不純物ドーピング領域と前記第2不純物ドーピング領域との差異が、前記共通ゲートに、前記第1FinFETと前記第2FinFETとの差異に関係した異なる仕事関数を与える、請求項3に記載の集積回路構造体。
- 前記第1フィンおよび前記第2フィンがほぼ同じ幅を有する、請求項1に記載の集積回路構造体。
- 相補的フィン型電界効果トランジスタ(FinFET)を用いる集積回路構造体であって、
第1フィンを有する第1型FinFETと、
前記第1フィンに並列に延在する第2フィンを有する第2型FinFETと、
前記第1型FinFETおよび前記第2型FinFETのソースおよびドレイン領域の間に配置された絶縁体フィンと、
を含み、
前記絶縁体フィンは、前記第1型FinFETと前記第2型FinFETとの間隔が1個のフィンの幅とほぼ等しくなるように、前記第1フィンおよび第2フィンとほぼ同じ寸法の幅を有し、
前記第1型FinFETおよび前記第2型FinFETのチャネル領域を覆うように共通ゲートが形成された、
集積回路構造体。 - 前記共通ゲートが、前記第1型FinFETに隣接する第1不純物ドーピング領域と、前記第2型FinFETに隣接する第2不純物ドーピング領域とを含む、請求項6に記載の集積回路構造体。
- 前記第1不純物ドーピング領域と前記第2不純物ドーピング領域との差異が、前記共通ゲートに、前記第1型FinFETと前記第2型FinFETとの差異に関係した異なる仕事関数を与える、請求項7に記載の集積回路構造体。
- 前記第1フィンおよび前記第2フィンがほぼ同じ幅を有する、請求項6に記載の集積回路構造体。
- 並列フィン型電界効果トランジスタ(FinFET)の対を形成する方法であって、
基板の上に半導体層を形成するステップと、
前記半導体層の上に、ほぼ垂直な側壁を有するマンドレル構造体を形成するステップと、
前記マンドレル構造体の前記側壁の上に、一連の3層のスペーサを形成するステップと、
前記マンドレル構造体と前記スペーサのうちの中間スペーサとを除去し、内側スペーサと外側スペーサとを前記半導体層から延びるように残すステップと、
前記内側スペーサおよび前記外側スペーサをマスクとして使用して前記半導体層にパターン形成し、前記内側スペーサおよび前記外側スペーサによって保護される領域が第1フィンおよび第2フィンとして前記基板から延びるように残すステップと、
前記第1フィンおよび前記第2フィンにチャネル領域を画定するステップと、
前記第1フィンおよび前記第2フィンの中央領域を覆うようにゲート導体を形成するステップと、
前記第1フィンおよび前記第2フィンの、前記ゲート導体により保護されない部分にドープして、前記第1フィンおよび第2フィンにソースおよびドレイン領域を形成するステップと、
前記第1フィンのソースおよびドレイン領域を、前記第2フィンのソースおよびドレイン領域から絶縁するステップと、
を含む方法。 - 前記一連の3層のスペーサを形成する前記ステップが、
前記マンドレル構造体の側壁に沿って前記内側スペーサを形成するステップと、
前記内側スペーサの上に前記中間スペーサを形成するステップと、
前記中間スペーサの上に前記外側スペーサを形成するステップと、
を含む、請求項10に記載の方法。 - 前記第1フィンが第1FinFETからなり、前記第2フィンが第2FinFETからなる、請求項10に記載の方法。
- 前記ソースおよびドレイン領域にドープする前記ステップにおいて、前記第1FinFETおよび前記第2FinFETのソースおよびドレイン領域に異なる角度で異なるドーパントを注入する、請求項12に記載の方法。
- 前記マンドレル構造体が2個の並列の側壁を含み、前記方法が前記側壁のそれぞれに隣接するFinFETの対を同時に形成する、請求項10に記載の方法。
- 前記除去するステップにおいて前記マンドレルおよび前記中間スペーサを1工程で除去するために、前記マンドレル構造体および前記中間スペーサを同じ材料により構成する、請求項10に記載の方法。
- 前記ソースおよびドレイン領域を絶縁する前記ステップが、前記第1フィンおよび前記第2フィンを覆うように誘電体材料を堆積するステップと、前記第1フィンおよび前記第2フィンの前記ソースおよびドレイン領域の間を除く全ての区域から前記誘電体材料を除去するステップとを含む、請求項10に記載の方法。
- 相補的並列フィン型電界効果トランジスタ(FinFET)の対を形成する方法であって、
基板の上に半導体層を形成するステップと、
前記半導体層の上に、ほぼ垂直な側壁を有するマンドレル構造体を形成するステップと、
前記マンドレル構造体の前記側壁の上に、一連の3層のスペーサを形成するステップと、
前記マンドレル構造体と前記スペーサのうちの中間スペーサとを除去し、内側スペーサと外側スペーサとを前記半導体層から延びるように残すステップと、
前記内側スペーサおよび前記外側スペーサをマスクとして使用して前記半導体層にパターン形成し、前記内側スペーサおよび前記外側スペーサによって保護される領域が第1フィンおよび第2フィンとして前記基板から延びるように残すステップと、
角度をつけた注入を使用して、前記第1フィンおよび前記第2フィンのチャネル領域に互いが異なるようにドープするステップと、
前記第1フィンおよび前記第2フィンの中央領域を覆うようにゲート導体を形成するステップと、
前記第1フィンおよび前記第2フィンの、前記ゲート導体により保護されない部分にドープして、前記第1フィンおよび第2フィンにソースおよびドレイン領域を形成するステップと、
前記第1フィンのソースおよびドレイン領域を、前記第2フィンのソースおよびドレイン領域から絶縁するステップと、
を含む方法。 - 前記チャネル領域にドープする前記ステップは、前記第1フィンが前記第2フィンを保護して該第2フィンが第1チャネル・ドーピング種を受容しないようにするために、前記第1フィンにほぼ垂直な角度から第1チャネル・ドーピング種を第1フィンにドープすることを含む、請求項17に記載の方法。
- 前記半導体層を形成する前記ステップが、前記半導体層の内部に第2チャネル・ドーピング種を与えることを含む、請求項18に記載の方法。
- 前記チャネル領域にドープする前記ステップはさらに、前記第2フィンが前記第1フィンを保護して該第1フィンが第2チャネル・ドーピング種を受容しないようにするために、前記第2フィンにほぼ垂直な角度から第2チャネル・ドーピング種を第2フィンにドープすることを含む、請求項18に記載の方法。
- 前記一連の3層のスペーサを形成する前記ステップが、
前記マンドレル構造体の側壁に沿って前記内側スペーサを形成するステップと、
前記内側スペーサの上に前記中間スペーサを形成するステップと、
前記中間スペーサの上に前記外側スペーサを形成するステップと、
を含む、請求項17に記載の方法。 - 前記ソースおよびドレイン領域にドープする前記ステップにおいて、前記第1フィンおよび前記第2フィンのソースおよびドレイン領域に異なる角度で異なるドーパントを注入する、請求項17に記載の方法。
- 前記マンドレル構造体は2個の並列の側壁を含み、前記側壁のそれぞれに隣接する複数の並列FinFETを同時に形成する、請求項17に記載の方法。
- 前記除去するステップにおいて前記マンドレルおよび前記中間スペーサを1工程で除去するために、前記マンドレル構造体および前記中間スペーサを同じ材料により構成する、請求項17に記載の方法。
- 前記ソースおよびドレイン領域を絶縁するプロセスが、前記第1フィンおよび前記第2フィンを覆うように誘電体材料を堆積するステップと、前記第1フィンおよび前記第2フィンの前記ソースおよびドレイン領域の間を除く全ての区域から前記誘電体材料を除去するステップとを含む、請求項17に記載の方法。
- 基板の上に並列フィン構造体を形成する方法であって、
半導体層の上にほぼ垂直な側壁を有するマンドレル構造体を形成するステップと、
前記マンドレル構造体の前記側壁の上に、一連の3層またはそれ以上のスペーサ層を形成するステップと、
前記マンドレル構造体と前記スペーサのうちの一つおきのスペーサとを除去し、内側スペーサと外側スペーサとを前記基板から延びるように残すステップと、
を含む方法。 - 前記内側スペーサおよび前記外側スペーサが、導体、半導体、絶縁体、および前記基板に構造体をパターン形成するために用いられるマスク要素の1つを含む、請求項26に記載の方法。
- 前記一連の3層のスペーサを形成する前記ステップが、
前記マンドレル構造体の側壁に沿って前記内側スペーサを形成するステップと、
前記内側スペーサの上に中間スペーサを形成するステップと、
前記中間スペーサの上に前記外側スペーサを形成するステップと、
を含む、請求項26に記載の方法。 - 前記内側スペーサが前記外側スペーサから1個のスペーサの幅だけ分離されるようにするために、スペーサは全て、ほぼ同じ幅を有する、請求項26に記載の方法。
- 基板の上に並列の構造体を形成する方法であって、
前記基板の上に材料層を形成するステップと、
前記材料層の上にほぼ垂直な側壁を有するマンドレル構造体を形成するステップと、
前記マンドレル構造体の前記側壁の上に、一連の3層のスペーサを形成するステップと、
前記マンドレル構造体と前記スペーサのうちの中間スペーサとを除去し、内側スペーサと外側スペーサとを前記材料層から延びるように残すステップと、
前記内側スペーサおよび前記外側スペーサをマスクとして使用して前記材料層にパターン形成し、前記内側スペーサおよび前記外側スペーサによって保護される領域が第1フィンおよび第2フィンとして前記基板から延びるように残すステップと、
を含む方法。 - 前記材料層が、導体、半導体および絶縁体の1つを含む、請求項30に記載の方法。
- 前記一連の3層のスペーサを形成する前記ステップが、
前記マンドレル構造体の側壁に沿って前記内側スペーサを形成するステップと、
前記内側スペーサの上に前記中間スペーサを形成するステップと、
前記中間スペーサの上に前記外側スペーサを形成するステップと、
を含む、請求項30に記載の方法。 - 前記内側スペーサが前記外側スペーサから1個のスペーサの幅だけ分離されるようにするために、スペーサは全て、ほぼ同じ幅を有する、請求項30に記載の方法。
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- 2004-06-30 DE DE602004015793T patent/DE602004015793D1/de not_active Expired - Lifetime
- 2004-06-30 KR KR1020067000044A patent/KR100792604B1/ko not_active IP Right Cessation
- 2004-06-30 EP EP04777432A patent/EP1639648B1/en not_active Expired - Lifetime
- 2004-06-30 WO PCT/US2004/021279 patent/WO2005004206A2/en active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
CN100483734C (zh) | 2009-04-29 |
US20050001273A1 (en) | 2005-01-06 |
US7517806B2 (en) | 2009-04-14 |
WO2005004206A3 (en) | 2005-02-17 |
DE602004015793D1 (de) | 2008-09-25 |
US20050272195A1 (en) | 2005-12-08 |
CN1846309A (zh) | 2006-10-11 |
US6943405B2 (en) | 2005-09-13 |
KR100792604B1 (ko) | 2008-01-09 |
EP1639648A2 (en) | 2006-03-29 |
ATE404996T1 (de) | 2008-08-15 |
WO2005004206A2 (en) | 2005-01-13 |
EP1639648B1 (en) | 2008-08-13 |
JP5041808B2 (ja) | 2012-10-03 |
KR20060031676A (ko) | 2006-04-12 |
EP1639648A4 (en) | 2007-05-30 |
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