JP2007524240A - 均一な臨界寸法のアクティブパターンで形成されたマルチゲートトランジスタ及びその製造方法 - Google Patents
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- E04G21/00—Preparing, conveying, or working-up building materials or building elements in situ; Other devices or measures for constructional work
- E04G21/12—Mounting of reinforcing inserts; Prestressing
- E04G21/122—Machines for joining reinforcing bars
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Architecture (AREA)
- Mechanical Engineering (AREA)
- Civil Engineering (AREA)
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- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Kunihiro Suzuki et al.,IEEE1993"Scaling Theory for Double―Gate SOIMOSFETs" Robert Chau,SSDM 2002,"Advanced Depleted―Substrate Transistors,Single―gate,Double―gate and Tri―gate" Z.Krivokapic,SSDM 2003,"High performance 45nm CMOS technology with 20nm multi―gate devices" Jeong―Hwan Yang,IEDM 2003,"Fully Working 6T―SRAM Cell with 45nm Gate Length Triple Gate Transistors"
12 アクティブ領域パターン
20 フォトレジストパターン
22 バー・パターン
30 ゲート電極
32 ホールプロファイル
36 位置
101 絶縁層
102 半導体層
102a アクティブパターン
105 絶縁ギャップ
110 フォトレジストパターン
115 エッチング停止膜
117 エピタキシャルマスク膜
117a エピタキシャルマスク
120 フォトレジストパターン
121 エピタキシ構造(エピタキシ層)
122 ゲート電極用導電膜
122a ゲート電極
130 フォトレジストパターン
201 絶縁層
202a アクティブパターン
217a エピタキシャルマスク
221 エピタキシ構造
222a ゲート電極
Claims (20)
- 少なくとも一つのアクティブパターンを形成して、
前記アクティブパターンの露出した領域から少なくとも一つのエピタキシ構造を成長させて、
前記アクティブパターンの少なくとも2個の面にチャネル領域を形成することを含むことを特徴とするマルチゲートトランジスタの製造方法。 - 前記アクティブパターンはラインパターンであって、
前記エピタキシ構造を成長させることは前記ラインパターンであるアクティブパターンの各末端から2個のエピタキシ構造を成長させることであって、
前記2個のエピタキシ構造にそれぞれソース及びドレインを形成することをさらに含むことを特徴とする請求項1に記載のマルチゲートトランジスタの製造方法。 - 前記アクティブパターンを形成することはそれぞれがメサ形態を有する複数のラインアクティブパターンを形成するものであって、
前記エピタキシ構造を成長させることは前記各アクティブパターンの末端から各エピタキシ構造を成長させることであることを特徴とする請求項1に記載のマルチゲートトランジスタの製造方法。 - 前記エピタキシ構造を成長させることは前記少なくとも2個のエピタキシ構造が相互に接触するように成長させることであることを特徴とする請求項3に記載のマルチゲートトランジスタの製造方法。
- 前記相互に接触するエピタキシ構造の第1セットにドレインを形成して、
前記相互に接触するエピタキシ構造の第2セットにソースを形成することをさらに含むことを特徴とする請求項4に記載のマルチゲートトランジスタの製造方法。 - 前記チャネル領域を形成することは前記少なくとも2個のアクティブパターンの表面に前記チャネル領域を形成するものであることを特徴とする請求項3に記載のマルチゲートトランジスタの製造方法。
- 前記アクティブパターンの中央領域に沿ってゲート絶縁膜及びゲート電極を形成することをさらに含むことを特徴とする請求項6に記載のマルチゲートトランジスタの製造方法。
- 前記各アクティブパターンの上面に、前記ゲート絶縁膜及びゲート電極を形成する前に、前記各アクティブパターンの2個の表面にチャネル領域を形成するための絶縁ギャップを形成することをさらに含むことを特徴とする請求項7に記載のマルチゲートトランジスタの製造方法。
- 前記アクティブパターンを形成することは
絶縁膜上に半導体層を形成して、
前記半導体層をアクティブパターンにパターニングすることを含むことを特徴とする請求項1に記載のマルチゲートトランジスタの製造方法。 - 前記アクティブパターンの露出した領域からエピタキシ構造を成長させる前にチャネル領域が形成されるアクティブパターンの領域上にエピタキシャルマスクを形成することをさらに含むことを特徴とする請求項1に記載のマルチゲートトランジスタの製造方法。
- 少なくとも一つのアクティブパターンと;
前記アクティブパターンから形成された少なくとも一つのエピタキシ構造;及び
前記アクティブパターンの少なくとも2個の面に形成されたチャネル領域を含むことを特徴とするマルチゲートトランジスタ。 - 前記アクティブパターンはラインパターンであって、
前記アクティブパターンの第1末端から形成された第1エピタキシ構造に形成されたドレイン;及び
前記アクティブパターンの第2末端から形成された第2エピタキシ構造に形成されたソースをさらに含むことを特徴とする請求項11に記載のマルチゲートトランジスタ。 - 前記アクティブパターンはそれぞれがメサ形態である複数のラインアクティブパターンであって、
前記少なくとも一つのエピタキシ構造は前記各アクティブパターンの末端から形成された構造であることを特徴とする請求項11に記載のマルチゲートトランジスタ。 - 前記少なくとも一つのエピタキシ構造は相互に接触する少なくとも2個のエピタキシ構造であることを特徴とする請求項13に記載のマルチゲートトランジスタ。
- 相互に接触する前記エピタキシ構造の第1セットに形成されたドレイン;及び
相互に接触する前記エピタキシ構造の第2セットに形成されたソースを含むことを特徴とする請求項12に記載のマルチゲートトランジスタ。 - 前記チャネル領域は前記少なくとも2個のアクティブパターンの表面に形成されたことを特徴とする請求項12に記載のマルチゲートトランジスタ。
- 前記アクティブパターンの中央領域に沿って形成されたゲート絶縁膜及びゲート電極をさらに含むことを特徴とする請求項16に記載のマルチゲートトランジスタ。
- 前記ゲート絶縁膜及びゲート電極を形成する前に前記各アクティブパターンの上面に形成された絶縁ギャップをさらに含むことを特徴とする請求項17に記載のマルチゲートトランジスタ。
- 前記アクティブパターンは絶縁膜上に形成されたことを特徴とする請求項11に記載のマルチゲートトランジスタ。
- 前記アクティブパターンは均一な臨界寸法を有することを特徴とする請求項11に記載のマルチゲートトランジスタ。
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KR1020040008148A KR100781538B1 (ko) | 2004-02-07 | 2004-02-07 | 성능이 향상된 멀티 게이트 트랜지스터용 액티브 구조의제조 방법, 이에 의해 제조된 액티브 구조 및 멀티 게이트트랜지스터 |
PCT/KR2005/000320 WO2005076340A1 (en) | 2004-02-07 | 2005-02-03 | Multi-gate transistor formed with active patterns of uniform critical dimension and fabricating method therefor |
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US (1) | US7244666B2 (ja) |
JP (1) | JP2007524240A (ja) |
KR (1) | KR100781538B1 (ja) |
CN (1) | CN100501947C (ja) |
DE (1) | DE112005000315T5 (ja) |
WO (1) | WO2005076340A1 (ja) |
Cited By (4)
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JP2012509601A (ja) * | 2008-12-24 | 2012-04-19 | インテル コーポレイション | 独立したソース及びドレイン設計を有するトライゲートsram、及びそれから成るデバイス |
JP2015159339A (ja) * | 2009-09-24 | 2015-09-03 | 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. | 金属ゲートとストレッサーを有するゲルマニウムフィンfet |
JP2018160704A (ja) * | 2018-07-18 | 2018-10-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10446655B2 (en) | 2014-08-22 | 2019-10-15 | Renesas Electronics Corporation | Semiconductor device |
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JP2018160704A (ja) * | 2018-07-18 | 2018-10-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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WO2005076340A1 (en) | 2005-08-18 |
DE112005000315T5 (de) | 2009-03-26 |
KR20050079843A (ko) | 2005-08-11 |
CN1926672A (zh) | 2007-03-07 |
US7244666B2 (en) | 2007-07-17 |
KR100781538B1 (ko) | 2007-12-03 |
CN100501947C (zh) | 2009-06-17 |
US20050173740A1 (en) | 2005-08-11 |
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