JP2007507111A - 高密度プラズマ化学蒸着を用いた間隙充填方法及び材料蒸着方法 - Google Patents
高密度プラズマ化学蒸着を用いた間隙充填方法及び材料蒸着方法 Download PDFInfo
- Publication number
- JP2007507111A JP2007507111A JP2006528102A JP2006528102A JP2007507111A JP 2007507111 A JP2007507111 A JP 2007507111A JP 2006528102 A JP2006528102 A JP 2006528102A JP 2006528102 A JP2006528102 A JP 2006528102A JP 2007507111 A JP2007507111 A JP 2007507111A
- Authority
- JP
- Japan
- Prior art keywords
- deposition
- substrate
- deuterium
- compound
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 97
- 239000000463 material Substances 0.000 title claims abstract description 40
- 238000007740 vapor deposition Methods 0.000 title claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 title claims description 10
- 230000008021 deposition Effects 0.000 claims abstract description 75
- 229910052805 deuterium Inorganic materials 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000000203 mixture Substances 0.000 claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims abstract description 19
- -1 deuterium compound Chemical class 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000005137 deposition process Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 77
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims description 42
- 239000007789 gas Substances 0.000 claims description 30
- 150000001875 compounds Chemical class 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000002243 precursor Substances 0.000 claims description 20
- 238000004544 sputter deposition Methods 0.000 claims description 19
- 229910052722 tritium Inorganic materials 0.000 claims description 13
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical group [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910004283 SiO 4 Inorganic materials 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 21
- 239000002019 doping agent Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000011800 void material Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 125000001424 substituent group Chemical group 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000001975 deuterium Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WRECIMRULFAWHA-UHFFFAOYSA-N trimethyl borate Chemical compound COB(OC)OC WRECIMRULFAWHA-UHFFFAOYSA-N 0.000 description 1
- WVLBCYQITXONBZ-UHFFFAOYSA-N trimethyl phosphate Chemical compound COP(=O)(OC)OC WVLBCYQITXONBZ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (44)
- 高密度プラズマ反応室内へ基板を供し、
重水素同位元素置換基をもつ少なくとも1種の化合物を前記反応室内へ供し、
前記反応室内で高密度プラズマを発生させ、及び
前記少なくとも1種の化合物の少なくとも一部を含む層を基板上へ化学蒸着させる各工程から構成される基板上への層蒸着方法。 - 前記重水素同位元素が重水素であることを特徴とする請求項1項記載の方法。
- 前記少なくとも1種の化合物がSiDxH4−x、Si2DyH6−y、PDzH3−z、SiCl2DH、SiCl2D2、SiO4C8DqH20−q、DH、及びD2(式中、x=1〜4、y=1〜6、Z=1〜3、及びq=1〜20)からなる群から選択される化合物であることを特徴とする請求項1項記載の方法。
- 前記層に酸化物材料が含まれることを特徴とする請求項1項記載の方法。
- 前記層が蒸着処理中に同時に蒸着及びエッチングされることを特徴とする請求項1項記載の方法。
- 前記蒸着によって実質的に平面状の表面が作製されることを特徴とする請求項1項記載の方法。
- 前記少なくとも1種の化合物が混合物から成り、前記混合物にさらO2及びO3の少なくとも一方が含まれることを特徴とする請求項1項記載の方法。
- 間隙構造が含まれる基板を供し、及び
少なくとも1種の重水素同位元素置換基をもつ少なくとも1種の前駆体を用いて、前記重水素の代わりに1Hを用いる場合よりも蒸着後における空隙の生成が少ない所定材料を前記基板上へ蒸着する各工程から構成される間隙充填方法。 - 前記間隙構造が前記基板内のトレンチから成ることを特徴とする請求項8項記載の方法。
- 前記間隙構造が隣接素子間の間隙から成ることを特徴とする請求項8項記載の方法。
- 前記間隙構造がトレンチである第一間隙構造であり、及び前記基板にさらに素子間の間隙である第二間隙構造が含まれ、及び所定材料の蒸着によって前記トレンチ及び前記素子間の間隙が実質的に充填されることを特徴とする請求項8項記載の方法。
- 前記少なくとも1種の前駆体がSiRxH4−x、Si2RyH6−y、PRzH3−z、SiCl2RH、SiCl2R2、SiO4C8RqH20−q(式中、Rは重水素、トリチウムまたはこれらの混合物であり、x=1〜4、Y=1〜6、Z=1〜3、及びq=1〜20)からなる群から選択される前駆体であることを特徴とする請求項8項記載の方法。
- 重水素化合物を含むガスの存在下で基板上への所定材料の蒸着及びエッチングを同時に行うことを特徴とする基板の充填部分の作製方法。
- 前記ガスに、前駆体成分及び、重水素化合物が含まれたスパッタリング成分が含まれることを特徴とする請求項13項記載の方法。
- 前記重水素化合物が第一重水素化合物であり、及び前記前駆体成分に第二重水素化合物が含まれることを特徴とする請求項14項記載の方法。
- 前記ガスに、重水素化合物が含まれた前駆体成分及びスパッタリング成分が含まれることを特徴とする請求項13項記載の方法。
- 前記ガスにD2、HD、DT、T2及びTHの少なくとも1種が含まれることを特徴とする請求項13項記載の方法。
- 前記ガスにさらにH2が含まれることを特徴とする請求項17項記載の方法。
- 前記充填部分に、トレンチ及び素子間空間から選択される少なくとも一つの形状が含まれることを特徴とする請求項13項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約1:1以上のアスペクト比を持つことを特徴とする請求項19項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約2:1以上のアスペクト比を持つことを特徴とする請求項19項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約3:1以上のアスペクト比を持つことを特徴とする請求項19項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約4:1以上のアスペクト比を持つことを特徴とする請求項19項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約5:1以上のアスペクト比を持つことを特徴とする請求項19項記載の方法。
- 前記少なくとも一つの形状の1または2以上が約10nm未満の幅を持つことを特徴とする請求項19項記載の方法。
- 蒸着処理がでこぼこ状の形状上に対して行われ、前記蒸着によってでこぼこ状の形状よりもより滑らかな面が形成されることを特徴とする請求項13項記載の方法。
- 前記材料が、硼素/リン酸でドープされた酸化珪素、フッ素でドープされた酸化珪素、リン酸でドープされた酸化珪素、硼素でドープされた酸化珪素及び未ドープの酸化珪素から選択されることを特徴とする請求項13項記載の方法。
- 蒸着処理中に重水素同位元素を含む少なくとも1種の化合物を与える処理を含んで構成され、及び所定材料の同時エッチング速度に対する前記材料の蒸着速度の比によって規定される、高密度プラズマ化学蒸着処理中における総合蒸着速度の制御方法。
- 前記少なくとも1種の化合物がスパッタリングガス中へ供給されることを特徴とする請求項28項記載の方法。
- 前記少なくとも1種の化合物が、D及びTの少なくとも一方をもつ二原子水素から選択されることを特徴とする請求項29項記載の方法。
- 前記蒸着がウェハーの表面全域において為され、及び前記ウェハー表面の中心点における前記総合蒸着速度が前記ウェハー表面の縁部における総合蒸着速度と実質的に同等であることを特徴とする請求項29項記載の方法。
- 前記中心点における前記総合蒸着速度が、前記中心点と前記ウェハー表面縁部にある点との間の線に沿った実質的にすべての点における総合蒸着速度と実質的に同等であることを特徴とする請求項31項記載の方法。
- 前記蒸着がウェハーの表面全体において起こり、及び前記ウェハー表面全体のいずれかの点における総合蒸着速度が、前記ウェハー表面全体の他のすべての点における総合蒸着速度と実質的に同等であることを特徴とする請求項29項記載の方法。
- 前記蒸着に1または2以上の間隙をもつ基板上への絶縁材料の蒸着が含まれ、前記蒸着によって前記絶縁材料で1または2以上の間隙が充填されて実質的に空隙のない充填間隙が形成されることを特徴とする請求項17項記載の方法。
- 前記総合蒸着速度が、同一蒸着条件下で少なくとも1種の化合物の1H体を用いた場合に生ずる対応総合蒸着速度よりも減じられることを特徴とする請求項17項記載の方法。
- 反応室内へ基板を供し、
前記反応室内へ少なくとも1種の重水素含有化合物を含むガス混合物を供し、及び
前記ガス混合物を反応させて層の蒸着とエッチングを同時に行うことにより、間隙内へ充填された材料に空隙がほぼない状態で高アスペクト比をもつ間隙を充填する材料から成る層を前記基板上へ形成する各工程から構成される半導体基板中の高アスペクト比をもつ間隙の充填方法。 - 前記反応室が高密度プラズマ化学蒸着室であることを特徴とする請求項36項記載の方法。
- 前記少なくとも1種の重水素含有化合物が、SiRxH4−x、Si2RyH6−y、PRzH3−z、SiCl2RH、SiCl2R2、SiO4C8RqH20−q、HR及びR2(式中、Rは重水素、トリチウムまたはこれらの混合物であり、X=1〜4、Y=1〜6、Z=1〜3及びq=1〜20)から選択されることを特徴とする請求項36項記載の方法。
- D2、HD、DT、T2及びTHから選択される少なくとも1種のガスの存在下で基板上へ所定材料を蒸着し、及び
前記蒸着を、前記材料の同時エッチング速度に対する前記材料の蒸着速度によって規定され、かつ実質的に同一条件下でのH2を用いた蒸着において生ずる対応する不均一の程度よりも基板表面全体における不均一の程度が明らかに改善された総合蒸着速度において実施する各工程から構成される、改善された蒸着速度均一性付与方法。 - 前記蒸着が高密度プラズマ蒸着であることを特徴とする請求項39項記載の方法。
- 前記少なくとも1種のガスを用いる際の前記不均一程度が、H2を用いる場合に生ずる不均一程度よりも少なくとも約18%改善されることを特徴とする請求項39項記載の方法。
- 前記蒸着が、約5kW未満の高周波数バイアス電力を用いる基板上への高密度プラズマ蒸着であることを特徴とする請求項39項記載の方法。
- 前記表面が直径200mmのウェハーから成ることを特徴とする請求項39項記載の方法。
- 前記表面が直径300mmのウェハーから成ることを特徴とする請求項39項記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/669,671 US7056833B2 (en) | 2003-09-23 | 2003-09-23 | Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition |
PCT/US2004/030875 WO2005031841A2 (en) | 2003-09-23 | 2004-09-20 | Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007507111A true JP2007507111A (ja) | 2007-03-22 |
JP4356747B2 JP4356747B2 (ja) | 2009-11-04 |
Family
ID=34313738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006528102A Active JP4356747B2 (ja) | 2003-09-23 | 2004-09-20 | 高密度プラズマ化学蒸着を用いた間隙充填方法及び材料蒸着方法 |
Country Status (8)
Country | Link |
---|---|
US (3) | US7056833B2 (ja) |
EP (1) | EP1665354B1 (ja) |
JP (1) | JP4356747B2 (ja) |
KR (1) | KR100759649B1 (ja) |
CN (1) | CN100454497C (ja) |
AT (1) | ATE537556T1 (ja) |
TW (1) | TWI248638B (ja) |
WO (1) | WO2005031841A2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7279770B2 (en) * | 2004-08-26 | 2007-10-09 | Micron Technology, Inc. | Isolation techniques for reducing dark current in CMOS image sensors |
US8021992B2 (en) * | 2005-09-01 | 2011-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | High aspect ratio gap fill application using high density plasma chemical vapor deposition |
US20130288485A1 (en) * | 2012-04-30 | 2013-10-31 | Applied Materials, Inc. | Densification for flowable films |
US20140070225A1 (en) * | 2012-09-07 | 2014-03-13 | Apple Inc. | Hydrogenation and Crystallization of Polycrystalline Silicon |
US9401423B2 (en) * | 2013-07-16 | 2016-07-26 | Globalfoundries Inc. | Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer |
CN105825906B (zh) * | 2016-03-30 | 2017-12-08 | 中国科学院上海应用物理研究所 | 一种放射性含氟废液水泥固化方法 |
US11508584B2 (en) | 2019-06-17 | 2022-11-22 | Applied Materials, Inc. | Deuterium-containing films |
CN114761612A (zh) * | 2019-12-02 | 2022-07-15 | 朗姆研究公司 | 原位pecvd覆盖层 |
US20240087882A1 (en) * | 2022-09-09 | 2024-03-14 | Applied Materials, Inc. | Fluorine-doped silicon-containing materials |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04268721A (ja) * | 1991-02-25 | 1992-09-24 | Canon Inc | 非単結晶炭化珪素半導体、及びその製造方法、及びそれを用いた半導体装置 |
JPH10303424A (ja) * | 1997-04-28 | 1998-11-13 | Lucent Technol Inc | 半導体デバイス |
JPH1187712A (ja) * | 1997-07-16 | 1999-03-30 | Internatl Business Mach Corp <Ibm> | 半導体処理で使用される重水素物質 |
US6077791A (en) * | 1996-12-16 | 2000-06-20 | Motorola Inc. | Method of forming passivation layers using deuterium containing reaction gases |
JP2000208526A (ja) * | 1999-01-14 | 2000-07-28 | Lucent Technol Inc | シリコン集積回路の製造方法 |
JP2000315791A (ja) * | 1999-05-06 | 2000-11-14 | Nec Corp | 半導体装置およびその製造方法 |
US6436195B1 (en) * | 1997-11-03 | 2002-08-20 | Zilog, Inc. | Method of fabricating a MOS device |
JP2002280382A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法及び製造装置 |
US20030012538A1 (en) * | 2001-07-12 | 2003-01-16 | Johnson Frederick G. | Use of deuterated gases for the vapor deposition of thin films for low-loss optical devices and waveguides |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6106678A (en) * | 1996-03-29 | 2000-08-22 | Lam Research Corporation | Method of high density plasma CVD gap-filling |
US6232216B1 (en) * | 1996-04-16 | 2001-05-15 | Nippon Telegraph And Telephone Corporation | Thin film forming method |
JP3599513B2 (ja) * | 1996-12-27 | 2004-12-08 | 松下電器産業株式会社 | 薄膜トランジスタの製造方法 |
US6025280A (en) | 1997-04-28 | 2000-02-15 | Lucent Technologies Inc. | Use of SiD4 for deposition of ultra thin and controllable oxides |
US5872058A (en) | 1997-06-17 | 1999-02-16 | Novellus Systems, Inc. | High aspect ratio gapfill process by using HDP |
US6395150B1 (en) | 1998-04-01 | 2002-05-28 | Novellus Systems, Inc. | Very high aspect ratio gapfill using HDP |
US6200911B1 (en) * | 1998-04-21 | 2001-03-13 | Applied Materials, Inc. | Method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps using differential plasma power |
US6030881A (en) | 1998-05-05 | 2000-02-29 | Novellus Systems, Inc. | High throughput chemical vapor deposition process capable of filling high aspect ratio structures |
US6255197B1 (en) * | 1998-06-10 | 2001-07-03 | Jim Mitzel | Hydrogen annealing method and apparatus |
US6129819A (en) * | 1998-11-25 | 2000-10-10 | Wafertech, Llc | Method for depositing high density plasma chemical vapor deposition oxide in high aspect ratio gaps |
US6368988B1 (en) | 1999-07-16 | 2002-04-09 | Micron Technology, Inc. | Combined gate cap or digit line and spacer deposition using HDP |
KR20010036046A (ko) * | 1999-10-05 | 2001-05-07 | 윤종용 | 중수소 가스를 포함하는 분위기를 사용하는 반도체 소자의 절연막 형성방법 |
US6331494B1 (en) | 1999-12-30 | 2001-12-18 | Novellus Systems, Inc. | Deposition of low dielectric constant thin film without use of an oxidizer |
US6670241B1 (en) | 2002-04-22 | 2003-12-30 | Advanced Micro Devices, Inc. | Semiconductor memory with deuterated materials |
US6768828B2 (en) * | 2002-11-04 | 2004-07-27 | Little Optics Inc. | Integrated optical circuit with dense planarized cladding layer |
US6982207B2 (en) * | 2003-07-11 | 2006-01-03 | Micron Technology, Inc. | Methods for filling high aspect ratio trenches in semiconductor layers |
-
2003
- 2003-09-23 US US10/669,671 patent/US7056833B2/en not_active Expired - Fee Related
-
2004
- 2004-09-20 JP JP2006528102A patent/JP4356747B2/ja active Active
- 2004-09-20 WO PCT/US2004/030875 patent/WO2005031841A2/en active Application Filing
- 2004-09-20 AT AT04784663T patent/ATE537556T1/de active
- 2004-09-20 EP EP04784663A patent/EP1665354B1/en active Active
- 2004-09-20 CN CNB2004800275649A patent/CN100454497C/zh active Active
- 2004-09-20 KR KR1020067005493A patent/KR100759649B1/ko active IP Right Grant
- 2004-09-22 TW TW093128729A patent/TWI248638B/zh active
-
2005
- 2005-04-25 US US11/115,854 patent/US7273793B2/en not_active Expired - Lifetime
-
2006
- 2006-01-27 US US11/341,199 patent/US7202183B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04268721A (ja) * | 1991-02-25 | 1992-09-24 | Canon Inc | 非単結晶炭化珪素半導体、及びその製造方法、及びそれを用いた半導体装置 |
US6077791A (en) * | 1996-12-16 | 2000-06-20 | Motorola Inc. | Method of forming passivation layers using deuterium containing reaction gases |
JPH10303424A (ja) * | 1997-04-28 | 1998-11-13 | Lucent Technol Inc | 半導体デバイス |
JPH1187712A (ja) * | 1997-07-16 | 1999-03-30 | Internatl Business Mach Corp <Ibm> | 半導体処理で使用される重水素物質 |
US6436195B1 (en) * | 1997-11-03 | 2002-08-20 | Zilog, Inc. | Method of fabricating a MOS device |
JP2000208526A (ja) * | 1999-01-14 | 2000-07-28 | Lucent Technol Inc | シリコン集積回路の製造方法 |
JP2000315791A (ja) * | 1999-05-06 | 2000-11-14 | Nec Corp | 半導体装置およびその製造方法 |
JP2002280382A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法及び製造装置 |
US20030012538A1 (en) * | 2001-07-12 | 2003-01-16 | Johnson Frederick G. | Use of deuterated gases for the vapor deposition of thin films for low-loss optical devices and waveguides |
Also Published As
Publication number | Publication date |
---|---|
TWI248638B (en) | 2006-02-01 |
EP1665354B1 (en) | 2011-12-14 |
KR20060095972A (ko) | 2006-09-05 |
US7202183B2 (en) | 2007-04-10 |
KR100759649B1 (ko) | 2007-09-17 |
TW200524008A (en) | 2005-07-16 |
WO2005031841A2 (en) | 2005-04-07 |
US7056833B2 (en) | 2006-06-06 |
US20060134924A1 (en) | 2006-06-22 |
US20050196976A1 (en) | 2005-09-08 |
US20050064729A1 (en) | 2005-03-24 |
CN1856870A (zh) | 2006-11-01 |
EP1665354A2 (en) | 2006-06-07 |
US7273793B2 (en) | 2007-09-25 |
CN100454497C (zh) | 2009-01-21 |
WO2005031841A3 (en) | 2005-09-01 |
JP4356747B2 (ja) | 2009-11-04 |
ATE537556T1 (de) | 2011-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11469107B2 (en) | Highly etch selective amorphous carbon film | |
CN110431661B (zh) | 用于用非晶硅膜对高深宽比沟槽进行间隙填充的两步工艺 | |
KR102513424B1 (ko) | 스페이서 및 하드마스크 애플리케이션을 위한 실란 및 알킬실란 종으로부터의 보란 매개 탈수소화 프로세스 | |
US9012302B2 (en) | Intrench profile | |
US6794290B1 (en) | Method of chemical modification of structure topography | |
US6030881A (en) | High throughput chemical vapor deposition process capable of filling high aspect ratio structures | |
US8133797B2 (en) | Protective layer to enable damage free gap fill | |
US7482247B1 (en) | Conformal nanolaminate dielectric deposition and etch bag gap fill process | |
US7202183B2 (en) | Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition | |
TW202126842A (zh) | 在反應空間中在基板上形成氮化矽薄膜的方法 | |
KR20160118961A (ko) | 3d nand 메모리 디바이스들에서의 개선된 수직 에칭 성능을 위한 막들의 플라즈마 강화 화학 기상 증착 | |
WO2013049223A2 (en) | Insensitive dry removal process for semiconductor integration | |
JP2004047996A (ja) | 窒素がドープされたシリコンカーバイド膜の蒸着方法 | |
KR20120057570A (ko) | 프로세스 챔버벽들 상의 실리콘 코팅을 사용하는 잔여 불소 라디칼들의 강화된 스캐빈징 | |
JPH04213829A (ja) | 半導体ウエハの段状表面にボイドを含まない酸化物層を形成する二段階法 | |
US7001854B1 (en) | Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures | |
KR100558999B1 (ko) | 기판 함몰부 충진 방법 | |
US11615966B2 (en) | Flowable film formation and treatments | |
EP0469791A1 (en) | Soluble oxides for integrated circuits | |
KR102453724B1 (ko) | 개선된 스텝 커버리지 유전체 | |
US11495454B2 (en) | Deposition of low-stress boron-containing layers | |
JP2022550057A (ja) | 高アスペクト比フィーチャの製造中に劣化を防止するためのマスク封入 | |
CN118176564A (zh) | 等离子体增强的成膜方法 | |
KR20080013269A (ko) | 반도체 소자 제조를 위한 박막형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060420 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20060922 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060420 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20070824 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20070824 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20071004 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090313 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090317 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090605 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20090605 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090714 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090727 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120814 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4356747 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130814 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |