JP2007293800A - 半導体装置とそれを用いたメモリカード - Google Patents
半導体装置とそれを用いたメモリカード Download PDFInfo
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- JP2007293800A JP2007293800A JP2006277884A JP2006277884A JP2007293800A JP 2007293800 A JP2007293800 A JP 2007293800A JP 2006277884 A JP2006277884 A JP 2006277884A JP 2006277884 A JP2006277884 A JP 2006277884A JP 2007293800 A JP2007293800 A JP 2007293800A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 22
- 238000005520 cutting process Methods 0.000 abstract description 24
- 238000009413 insulation Methods 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 9
- 230000007423 decrease Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 16
- 239000010410 layer Substances 0.000 description 15
- 230000020169 heat generation Effects 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 10
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 7
- 238000003763 carbonization Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0256—Electrical insulation details, e.g. around high voltage areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
- H05K2201/0761—Insulation resistance, e.g. of the surface of the PCB between the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
- Credit Cards Or The Like (AREA)
Abstract
【解決手段】回路基板2の第1の主面2aには外部接続端子8が設けられており、第2の主面2bには半導体素子13、14が実装されている。回路基板2の第1の主面2aには、外部接続端子8の形成領域を除く領域に第1の配線網9が設けられている。回路基板2の第2の主面2bには第2の配線網11が設けられている。配線網9、11は曲線部を含む切り欠き部5やくびれ部6を有する辺4Aからの距離が他の辺(3A、3B、4B)からの距離より離れて形成されている。
【選択図】図2
Description
Claims (5)
- 第1の主面と前記第1の主面とは反対側の第2の主面とを有し、かつ外形の少なくとも一辺に曲線部が設けられた基板と、
前記基板の前記第1の主面および前記第2の主面の少なくとも一方の主面に実装された半導体素子と、
前記基板の前記第1の主面および前記第2の主面の少なくとも一方に設けられ、前記曲線部を有する辺からの距離が他の辺からの距離より離れている配線網と
を具備することを特徴とする半導体装置。 - 第1の主面と前記第1の主面とは反対側の第2の主面とを有し、かつ外形の少なくとも一辺に曲線部が設けられた基板と、
前記基板の前記第1の主面に形成された外部接続端子と、
前記基板の前記第1の主面における前記外部接続端子の形成領域を除く領域に設けられ、前記曲線部を有する辺からの距離が他の辺からの距離より離れている第1の配線網と、
前記第1の配線網を覆うように、前記基板の前記第1の主面に形成された絶縁層と、
前記基板の前記第2の主面に設けられ、前記曲線部を有する辺からの距離が他の辺からの距離より離れている第2の配線網と、
前記基板の前記第2の主面に実装された半導体素子と、
前記半導体素子を封止するように、前記基板の前記第2の主面上に設けられた封止樹脂層と
を具備することを特徴とする半導体装置。 - 請求項1または請求項2記載の半導体装置において、
前記配線網は前記基板の前記曲線部を有する辺から0.5mm以上離れて形成されていることを特徴とする半導体装置。 - 請求項1ないし請求項3のいずれか1項記載の半導体装置において、
前記基板は前記曲線部を有する辺と前記配線網との間に設けられたダミー配線を有することを特徴とする半導体装置。 - 請求項2ないし請求項4のいずれか1項記載の半導体装置のみで構成されていることを特徴とするメモリカード。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006277884A JP4843447B2 (ja) | 2006-03-31 | 2006-10-11 | 半導体装置とそれを用いたメモリカード |
US11/691,716 US7679174B1 (en) | 2006-03-31 | 2007-03-27 | Semiconductor device and memory card using the same |
TW096110836A TW200810025A (en) | 2006-03-31 | 2007-03-28 | Semiconductor device and memory card using the same |
US12/693,096 US8110434B2 (en) | 2006-03-31 | 2010-01-25 | Semiconductor device and memory card using the same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006098271 | 2006-03-31 | ||
JP2006098271 | 2006-03-31 | ||
JP2006277884A JP4843447B2 (ja) | 2006-03-31 | 2006-10-11 | 半導体装置とそれを用いたメモリカード |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007293800A true JP2007293800A (ja) | 2007-11-08 |
JP4843447B2 JP4843447B2 (ja) | 2011-12-21 |
Family
ID=38557572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006277884A Active JP4843447B2 (ja) | 2006-03-31 | 2006-10-11 | 半導体装置とそれを用いたメモリカード |
Country Status (3)
Country | Link |
---|---|
US (2) | US7679174B1 (ja) |
JP (1) | JP4843447B2 (ja) |
TW (1) | TW200810025A (ja) |
Cited By (5)
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JP2009259207A (ja) * | 2008-03-21 | 2009-11-05 | Toshiba Corp | 半導体メモリカードとそれに用いられる半導体メモリデバイス |
JP2009259940A (ja) * | 2008-04-15 | 2009-11-05 | Toshiba Corp | 半導体パッケージ |
US7855446B2 (en) | 2008-10-31 | 2010-12-21 | Kabushiki Kaisha Toshiba | Semiconductor memory device and semiconductor memory card |
US7952183B2 (en) | 2007-10-29 | 2011-05-31 | Kabushiki Kaisha Toshiba | High capacity memory with stacked layers |
JP2016026411A (ja) * | 2008-02-08 | 2016-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP2009157628A (ja) * | 2007-12-26 | 2009-07-16 | Toshiba Corp | 半導体メモリカード |
JP4523051B2 (ja) * | 2008-05-09 | 2010-08-11 | 日東電工株式会社 | 配線回路基板の製造方法 |
US8472199B2 (en) * | 2008-11-13 | 2013-06-25 | Mosaid Technologies Incorporated | System including a plurality of encapsulated semiconductor chips |
JP5345023B2 (ja) * | 2009-08-28 | 2013-11-20 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
JP5269747B2 (ja) * | 2009-10-30 | 2013-08-21 | 株式会社東芝 | 半導体記憶装置 |
US8724339B2 (en) * | 2009-12-01 | 2014-05-13 | Apple Inc. | Compact media player |
US8649820B2 (en) | 2011-11-07 | 2014-02-11 | Blackberry Limited | Universal integrated circuit card apparatus and related methods |
US8936199B2 (en) | 2012-04-13 | 2015-01-20 | Blackberry Limited | UICC apparatus and related methods |
USD703208S1 (en) | 2012-04-13 | 2014-04-22 | Blackberry Limited | UICC apparatus |
USD701864S1 (en) | 2012-04-23 | 2014-04-01 | Blackberry Limited | UICC apparatus |
US9071018B2 (en) | 2013-11-11 | 2015-06-30 | Sang Moon Suh | Removable media with latch |
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US20150357280A1 (en) * | 2014-06-06 | 2015-12-10 | Kabushiki Kaisha Toshiba | Memory card and method for manufacturing the same |
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USD773466S1 (en) * | 2015-08-20 | 2016-12-06 | Isaac S. Daniel | Combined secure digital memory and subscriber identity module |
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KR102440366B1 (ko) * | 2018-01-04 | 2022-09-05 | 삼성전자주식회사 | 메모리 카드 및 이를 포함하는 전자 장치 |
USD934868S1 (en) * | 2018-02-28 | 2021-11-02 | Sony Corporation | Memory card |
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2006
- 2006-10-11 JP JP2006277884A patent/JP4843447B2/ja active Active
-
2007
- 2007-03-27 US US11/691,716 patent/US7679174B1/en active Active
- 2007-03-28 TW TW096110836A patent/TW200810025A/zh unknown
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2010
- 2010-01-25 US US12/693,096 patent/US8110434B2/en active Active
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JPH03176972A (ja) * | 1989-12-05 | 1991-07-31 | Teikoku Tsushin Kogyo Co Ltd | フレキシブル基板の端子接続構造 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7952183B2 (en) | 2007-10-29 | 2011-05-31 | Kabushiki Kaisha Toshiba | High capacity memory with stacked layers |
JP2016026411A (ja) * | 2008-02-08 | 2016-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2009259207A (ja) * | 2008-03-21 | 2009-11-05 | Toshiba Corp | 半導体メモリカードとそれに用いられる半導体メモリデバイス |
US8274141B2 (en) | 2008-03-21 | 2012-09-25 | Kabushiki Kaisha Toshiba | Semiconductor memory card and semiconductor memory device |
JP2009259940A (ja) * | 2008-04-15 | 2009-11-05 | Toshiba Corp | 半導体パッケージ |
US7855446B2 (en) | 2008-10-31 | 2010-12-21 | Kabushiki Kaisha Toshiba | Semiconductor memory device and semiconductor memory card |
US8080868B2 (en) | 2008-10-31 | 2011-12-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device and semiconductor memory card |
US8288855B2 (en) | 2008-10-31 | 2012-10-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device and semiconductor memory card |
Also Published As
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TWI337391B (ja) | 2011-02-11 |
US8110434B2 (en) | 2012-02-07 |
US20070228509A1 (en) | 2007-10-04 |
US20100120203A1 (en) | 2010-05-13 |
TW200810025A (en) | 2008-02-16 |
JP4843447B2 (ja) | 2011-12-21 |
US7679174B1 (en) | 2010-03-16 |
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