JP2007201023A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2007201023A JP2007201023A JP2006015610A JP2006015610A JP2007201023A JP 2007201023 A JP2007201023 A JP 2007201023A JP 2006015610 A JP2006015610 A JP 2006015610A JP 2006015610 A JP2006015610 A JP 2006015610A JP 2007201023 A JP2007201023 A JP 2007201023A
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- semiconductor device
- passive component
- base substrate
- die pad
- electrode terminals
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Abstract
【解決手段】受動部品15は、電極端子16、16の上下方向の高さが、素体部17の高さよりも高く形成されている。より詳しくは、電極端子16、16の断面積は、素体部17の断面積よりも若干大きく形成されている。これにより電極端子16、16の上部および下部が、素体部17よりも若干高くなるように(はみだすように)位置している。受動部品15は、素体部17が接着剤33を介して高位部28に基板面と略平行になるように固着されており、電極端子16、16の一部(下端部)は、凹部27、27内の空間にそれぞれ位置する。これにより、電極端子16、16とダイパッド21との間に所定の間隙が形成されている。
【選択図】図6
Description
これにより、導体パターン部の面積を縮小でき、半導体装置を小型化することができる。また、導体パターンを介することなくボンディングワイヤにより半導体チップと受動部品とを相互に接続するため、半導体装置の動作をより安定させ、電気特性を向上させることができる。
(1)ダイパッド上にディスペンサ等により塗布供給されたペースト状の絶縁性接着剤上に、受動部品を載置する際、係る受動部品に付与する荷重が過大になった場合には、受動部品の電極端子とダイパッドとが接触してショートしてしまう場合がある。
また、本発明では上記課題を解決するために、柱状の本体部と前記本体部の軸方向の両端部にそれぞれ設けられた一対の電極端子を備える受動部品と、半導体素子とをワイヤボンディングにて接続して構成される半導体装置の製造方法であって、ベース基板用基材に凹部を形成してベース基板を得る工程と、前記凹部に接着部材を供給する工程と、前記本体部が前記接着部材を介して前記ベース基板上に位置し、前記電極端子がそれぞれ前記接着部材を介して前記凹部に対応する部位に位置するように前記受動部品を配設する工程と、前記受動部品に所定の圧力を加えることにより前記受動部品と前記ベース基板とを仮接着する工程と、前記接着部材を硬化させて前記受動部品と前記ベース基板とを本接着する工程と、を有することを特徴とする半導体装置の製造方法が提供される。
図1は、実施の形態の半導体装置を示す斜視図である。
半導体装置10は、SOP(Small Outline Package)タイプのLSIパッケージであり、後述する半導体素子をリードフレームに設置して電気絶縁性を備える封止部材30にて封止されている。また、封止部材30の両側面には、それぞれ半導体素子に電気的に接続された4本のアウターリード23が設けられている。封止部材30の構成材料としては、例えばエポキシ樹脂等が挙げられる。
なお、以下では図2中の上側を「上」、下側を「下」、右側を「右」という。
半導体装置10は、半導体素子11と、受動部品15と、複数のワイヤ(ボンディングワイヤ)18と、ダイパッド(ベース基板)21とダイパッド21の周囲に設けられた複数のインナーリード22とアウターリード23と一対の支持部24、24とを備えるリードフレーム20とを有している。
半導体素子11は、ダイパッド21上に層状の接着剤32を介して配置されている。また、半導体素子11は、その表面上に配設された複数の電極パッド12を備えている。
図3は、受動部品を示す斜視図である。
ワイヤ18は、例えば金、アルミニウム等の金属で構成されている。
図6に示すように受動部品15は、電極端子16、16の図6中上下方向の長さ(以下、高さという)が、素体部17の高さよりも高く形成されている。より詳しくは、電極端子16、16の断面積は、素体部17の断面積よりも若干大きく形成されている。これにより電極端子16、16の上部および下部が、素体部17よりも若干高くなるように(はみだすように)位置している。
図7は、第1の実施の形態の半導体装置のリードフレームの変形例を示す図であり、図7(a)は、半導体装置のリードフレームを示す平面図であり、図7(b)は、図7(a)に示すリードフレームのA−A線での断面図であり、図7(c)は、図7(a)に示すリードフレームのB−B線での断面図である。
図8〜図10は、第1の実施の形態の半導体装置の製造方法を示す断面図である。
次に、図9(b)に示すように、接着剤32を介してダイパッド21と半導体素子11とを接着(固着)する。
次に、図9(d)および図9(d1)に示すように、受動部品15を、素体部17が高位部28上に位置し、電極端子16、16がそれぞれ凹部27、27上に位置するように配設し、受動部品15とダイパッド21とを未硬化の接着剤33を介して仮接着する。このとき受動部品15に図中矢印で示す方向に所定の圧力を加えることにより、受動部品15が安定する。ここで、受動部品15に加える圧力は、接着剤33の粘度に応じて適宜調整され、例えば0.5N〜4N程度である。
次に、図10(f)に示すように、ワイヤ18を用いて半導体素子11と各電極端子16とをそれぞれ接続する。
次に、図示しないアウターリードの整形加工を行う。
以上で半導体装置10が完成する。
図11は、第2の実施の形態の半導体装置を示す断面図である。
なお、以下の図面では、図面を見やすくするため封止部材30の図示を省略している。
半導体装置10aは、リードフレーム20a(ダイパッド21a)の構成が第1の実施の形態のリードフレーム20(ダイパッド21)と異なっている。
そしてダイパッド21aの、右側の(他方の)電極端子16に対応する部位はグラウンド電位に接続されている。よって、右側の電極端子16がグラウンド電位に接続されている場合は、右側の電極端子16がダイパッド21aに接触した場合でも凹部27によってダイパッド21aと左側の電極端子16とは離間されているため、右側の電極端子16と左側の電極端子16とのショートを防止することができ、受動部品15の動作機能が損なわれることを防止できる。
次に、半導体装置の第3の実施の形態について説明する。
半導体装置10bは、リードフレーム20b(ダイパッド21b)の構成が第1の実施の形態のリードフレーム20(ダイパッド21)と異なっている。
図13に示すように、素体部17が接着剤33を介して高位部28aに支持されることにより電極端子16、16とダイパッド21bの電極端子16、16にそれぞれ対応する部位27a、27aとの間に所定の間隙が形成されている。
次に、半導体装置の第4の実施の形態について説明する。
半導体装置10cは、リードフレーム20c(ダイパッド21c)の構成が第3の実施の形態のリードフレーム20b(ダイパッド21b)と異なっている。
図15は、第4の実施の形態の半導体装置を示す断面図である。
素体部17が接着剤33を介して高位部28b、28bに支持されることにより電極端子16、16とダイパッド21cの電極端子16、16にそれぞれ対応する部位27b、27bとの間に所定の間隙が形成されている。
図16は、第5の実施の形態の半導体装置のリードフレームを示す図であり、図16(a)は、半導体装置のリードフレームを示す平面図であり、図16(b)は、図16(a)に示すリードフレームのA−A線での断面図であり、図16(c)は、図16(a)に示すリードフレームのB−B線での断面図であり、図16(d)は、図16(a)に示すリードフレームのC−C線での断面図である。
半導体装置10dは、リードフレーム20d(ダイパッド21d)の構成が第1の実施の形態のリードフレーム20(ダイパッド21)と異なっている。
図17は、第5の実施の形態の半導体装置を示す断面図であり、図18は、第5の実施の形態の半導体装置の受動部品の配置を説明する平面図である。
図19は、第6の実施の形態の半導体装置のリードフレームを示す図であり、図19(a)は、半導体装置のリードフレームを示す平面図であり、図19(b)は、図19(a)に示すリードフレームのA−A線での断面図であり、図19(c)は、図19(a)に示すリードフレームのB−B線での断面図であり、図19(d)は、図19(a)に示すリードフレームのC−C線での断面図である。
半導体装置10eは、リードフレーム20e(ダイパッド21e)の構成が第1の実施の形態のリードフレーム20(ダイパッド21)と異なっている。
図20は、第6の実施の形態の半導体装置の受動部品の配置を説明する平面図である。
図21は、第7の実施の形態の半導体装置の内部を示す平面図であり、図22は、図21に示す半導体装置のリードフレームを示す図であり、図22(a)は、半導体装置のリードフレームを示す平面図であり、図22(b)は、図22(a)に示すリードフレームのA−A線での断面図であり、図22(c)は、図22(a)に示すリードフレームのB−B線での断面図である。
図21に示す半導体装置10fは、リードフレーム20f(ダイパッド21f)の構成が第1の実施の形態のリードフレーム20(ダイパッド21)と異なっている。
図23は、第8の実施の形態の半導体装置の内部を示す平面図である。
以下、第8の実施の形態の半導体装置10gについて、前述した第1の実施の形態との相違点を中心に説明し、同様の事項については、その説明を省略する。
ダイパッド21gの電極端子16、16に対応する部位には、それぞれ開口26、26が設けられている。
ダイパッド21gの下面には開口26、26を覆うように樹脂製のフィルム部材35が接着されている。そして本実施の形態の受動部品15は、素体部17が高位部28上に位置するように、フィルム部材35上に配設された接着剤33を介してダイパッド21g上に固着されている。
図26は、第9の実施の形態の半導体装置の内部を示す平面図であり、図26(a)は、半導体装置のリードフレームを示す平面図であり、図26(b)は、図26(a)に示すリードフレームのA−A線での断面図であり、図26(c)は、図26(a)に示すリードフレームのB−B線での断面図である。また、図27は、図26に示す半導体装置のリードフレームを示す図である。
半導体装置10hは、リードフレーム20h(ダイパッド21h)の構成が第2の実施の形態のリードフレーム20a(ダイパッド21a)と異なっている。
以上、本発明の半導体装置および半導体装置の製造方法を、図示の実施の形態に基づいて説明したが、本発明はこれに限定されるものではなく、各部の構成は、同様の機能を有する任意の構成のものに置換することができる。また、本発明に、他の任意の構成物や工程が付加されていてもよい。
なお、前述した各実施の形態ではSOPタイプのLSIパッケージについて説明したが、本発明はこれに限らずSOJ(Small Out-line J-leaded Package)やQFP(Quad Flat Package)タイプのLSIパッケージに対しても適用することができる。さらに、本発明はリードフレーム型の半導体装置に限らず半導体チップおよび受動部品を搭載(設置)するダイパッド部が導体で構成される半導体装置全般に適用することができる。
(付記1) 電気絶縁性の封止材により封止された半導体装置において、
絶縁性を備える柱状の本体部と、前記本体部の軸方向の両端部にそれぞれ設けられた一対の電極端子とを有する受動部品と、
少なくとも1つの前記電極端子にボンディングワイヤを介して接続された半導体素子と、
前記受動部品と前記半導体素子とがそれぞれ接着層を介して載置され、前記本体部が基板面と略平行になるように支持し、かつ、前記電極端子に接触しないように形成された部位を有するベース基板と、
を備えることを特徴とする半導体装置。
(付記3) 前記凹部は、前記電極端子のそれぞれに対応する部位に複数形成されていることを特徴とする付記2記載の半導体装置。
(付記5) 前記ベース基板の前記本体部に対応する部位に凸部が形成されていることを特徴とする付記1記載の半導体装置。
(付記7) 前記ベース基板の前記受動部品に対応する部位に凹部が形成され、前記凹部内の前記本体部に対応する部位に前記凹部の深さよりも高さの低い凸部が形成されていることを特徴とする付記1記載の半導体装置。
(付記9) 前記ベース基板の略全面に亘って複数の凹凸が形成されていることを特徴とする付記1記載の半導体装置。
(付記11) 前記複数の凹凸は、前記ベース基板の前記半導体素子が載置される面の反対面側にも形成されていることを特徴とする付記9記載の半導体装置。
(付記13) 前記ベース基板の前記半導体素子が載置される面の反対面側に前記開口を覆うように形成された樹脂部材が配設されていることを特徴とする付記12記載の半導体装置。
(付記15) 柱状の本体部と前記本体部の軸方向の両端部にそれぞれ設けられた一対の電極端子を備える受動部品と、半導体素子とをワイヤボンディングにて接続して構成される半導体装置の製造方法であって、
ベース基板用基材に凹部を形成してベース基板を得る工程と、
前記凹部に接着部材を供給する工程と、
前記本体部が前記接着部材を介して前記ベース基板上に位置し、前記電極端子がそれぞれ前記接着部材を介して前記凹部に対応する部位に位置するように前記受動部品を配設する工程と、
前記受動部品に所定の圧力を加えることにより前記受動部品と前記ベース基板とを仮接着する工程と、
前記接着部材を硬化させて前記受動部品と前記ベース基板とを本接着する工程と、
を有することを特徴とする半導体装置の製造方法。
11 半導体素子
12 電極パッド
15 受動部品
16 電極端子
17 素体部
18 ワイヤ
20、20a〜20h リードフレーム
21、21a〜21h ダイパッド(ベース基板)
22 インナーリード
23 アウターリード
24 支持部
25 切り欠き部
26 開口
27、27c 凹部
27a、27b 部位
28、28a〜28c 高位部
29、29a ガイド部
30 封止部材
32 接着剤
33 接着剤(絶縁性接着剤)
35 フィルム部材
200、210 ノズル
211 凹部(段差部)
Claims (10)
- 電気絶縁性の封止材により封止された半導体装置において、
絶縁性を備える柱状の本体部と、前記本体部の軸方向の両端部にそれぞれ設けられた一対の電極端子とを有する受動部品と、
少なくとも1つの前記電極端子にボンディングワイヤを介して接続された半導体素子と、
前記受動部品と前記半導体素子とがそれぞれ接着層を介して載置され、前記本体部が基板面と略平行になるように支持し、かつ、前記電極端子に接触しないように形成された部位を有するベース基板と、
を備えることを特徴とする半導体装置。 - 前記ベース基板の前記電極端子に対応する部位に凹部が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記凹部は、前記電極端子のそれぞれに対応する部位に複数形成されていることを特徴とする請求項2記載の半導体装置。
- 前記凹部は、前記電極端子のいずれか一方に形成されていることを特徴とする請求項2記載の半導体装置。
- 前記ベース基板の前記本体部に対応する部位に凸部が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記凸部は、前記本体部の長手方向に沿って複数形成されていることを特徴とする請求項5記載の半導体装置。
- 前記ベース基板の前記受動部品に対応する部位に凹部が形成され、前記凹部内の前記本体部に対応する部位に前記凹部の深さよりも高さの低い凸部が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記受動部品の長手方向に略直交する方向への移動を規制するガイド部が設けられていることを特徴とする請求項2記載の半導体装置。
- 前記ベース基板の前記電極端子に対応する部位に開口が形成されていることを特徴とする請求項1記載の半導体装置。
- 柱状の本体部と前記本体部の軸方向の両端部にそれぞれ設けられた一対の電極端子を備える受動部品と、半導体素子とをワイヤボンディングにて接続して構成される半導体装置の製造方法であって、
ベース基板用基材に凹部を形成してベース基板を得る工程と、
前記凹部に接着部材を供給する工程と、
前記本体部が前記接着部材を介して前記ベース基板上に位置し、前記電極端子がそれぞれ前記接着部材を介して前記凹部に対応する部位に位置するように前記受動部品を配設する工程と、
前記受動部品に所定の圧力を加えることにより前記受動部品と前記ベース基板とを仮接着する工程と、
前記接着部材を硬化させて前記受動部品と前記ベース基板とを本接着する工程と、
を有することを特徴とする半導体装置の製造方法。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012009904A (ja) * | 2008-10-30 | 2012-01-12 | Denso Corp | 半導体装置 |
JP2013232552A (ja) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
JP2013232551A (ja) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
JP2015130492A (ja) * | 2013-12-05 | 2015-07-16 | ローム株式会社 | 半導体モジュール |
JP2016157988A (ja) * | 2016-06-09 | 2016-09-01 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
JP2017143317A (ja) * | 2017-05-25 | 2017-08-17 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004356494A (ja) * | 2003-05-30 | 2004-12-16 | Hitachi Ltd | 電子装置および圧力検出装置 |
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US10615105B2 (en) * | 2017-10-20 | 2020-04-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
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US11201065B2 (en) | 2019-10-31 | 2021-12-14 | Texas Instruments Incorporated | Testing semiconductor components |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10256466A (ja) * | 1997-03-14 | 1998-09-25 | Nittetsu Semiconductor Kk | 半導体装置 |
JP2002231875A (ja) * | 2001-02-05 | 2002-08-16 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2004047811A (ja) * | 2002-07-12 | 2004-02-12 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2005286057A (ja) * | 2004-03-29 | 2005-10-13 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2504486B2 (ja) | 1987-10-12 | 1996-06-05 | 富士通株式会社 | 混成集積回路構造 |
JPH08162607A (ja) | 1994-12-07 | 1996-06-21 | Matsushita Electric Ind Co Ltd | 半導体素子 |
JPH1154880A (ja) | 1997-08-05 | 1999-02-26 | Fujitsu Ten Ltd | 電子部品の構造及び電子部品の実装構造 |
JP4233776B2 (ja) * | 2001-09-12 | 2009-03-04 | 株式会社村田製作所 | 回路形成基板 |
JP3891048B2 (ja) | 2002-06-17 | 2007-03-07 | 松下電器産業株式会社 | モジュール部品の製造方法およびそれに用いられるマスキングチップ |
CN2681524Y (zh) * | 2004-01-21 | 2005-02-23 | 威盛电子股份有限公司 | 线路载板 |
JP2005277355A (ja) * | 2004-03-26 | 2005-10-06 | Sanyo Electric Co Ltd | 回路装置 |
JP4814639B2 (ja) * | 2006-01-24 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
-
2006
- 2006-01-24 JP JP2006015610A patent/JP4814639B2/ja not_active Expired - Fee Related
- 2006-04-11 TW TW095112825A patent/TWI305038B/zh not_active IP Right Cessation
- 2006-04-27 CN CN2006100771832A patent/CN101009269B/zh not_active Expired - Fee Related
- 2006-05-01 US US11/414,485 patent/US7528460B2/en not_active Expired - Fee Related
- 2006-05-04 KR KR1020060040456A patent/KR100724713B1/ko not_active IP Right Cessation
-
2009
- 2009-04-06 US US12/418,906 patent/US8048719B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10256466A (ja) * | 1997-03-14 | 1998-09-25 | Nittetsu Semiconductor Kk | 半導体装置 |
JP2002231875A (ja) * | 2001-02-05 | 2002-08-16 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP2004047811A (ja) * | 2002-07-12 | 2004-02-12 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2005286057A (ja) * | 2004-03-29 | 2005-10-13 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012009904A (ja) * | 2008-10-30 | 2012-01-12 | Denso Corp | 半導体装置 |
US10622944B2 (en) | 2012-04-27 | 2020-04-14 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
JP2013232551A (ja) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
US9787250B2 (en) | 2012-04-27 | 2017-10-10 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US10243515B2 (en) | 2012-04-27 | 2019-03-26 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US10615108B2 (en) | 2012-04-27 | 2020-04-07 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
JP2013232552A (ja) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | 半導体装置及び計測機器 |
US20200235046A1 (en) * | 2012-04-27 | 2020-07-23 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
US11309234B2 (en) | 2012-04-27 | 2022-04-19 | Lapis Semiconductor Co., Ltd. | Semiconductor device having an oscillator and an associated integrated circuit |
US11854952B2 (en) | 2012-04-27 | 2023-12-26 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
JP2015130492A (ja) * | 2013-12-05 | 2015-07-16 | ローム株式会社 | 半導体モジュール |
JP2016157988A (ja) * | 2016-06-09 | 2016-09-01 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
JP2017143317A (ja) * | 2017-05-25 | 2017-08-17 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
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TW200729449A (en) | 2007-08-01 |
US8048719B2 (en) | 2011-11-01 |
CN101009269A (zh) | 2007-08-01 |
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