JP2007123823A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 239000002344 surface layer Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 31
- 239000004642 Polyimide Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 229920001721 polyimide Polymers 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 46
- 230000000694 effects Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920005548 perfluoropolymer Polymers 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
【解決手段】埋め込み酸化膜3上にあるSOI層1aの表層部に、横型MOSトランジスタ(LDMOS)が形成されてなる半導体装置10であって、シリコン(Si)より誘電率の低い低誘電率領域5が、埋め込み酸化膜3に当接して、LDMOSのソースSとドレインDの間で形成されてなる半導体装置とする。
【選択図】図1
Description
(数式1) V ∝ (ts/2+3tox)・ts/ε0
数式1において、tsはSOI層1aの厚さ、toxは埋め込み酸化膜3の膜厚、ε0は埋め込み酸化膜3の誘電率である。従って、数式1からわかるように、縦方向の耐圧は、SOI層1aの厚さts、埋め込み酸化膜3の膜厚toxおよび埋め込み酸化膜3の誘電率ε0で決まってしまう。従って、寸法設計により半導体装置9bの耐圧を向上させるためには、SOI層1aの厚さtsを厚くするか、埋め込み酸化膜3の膜厚toxを厚くする必要がある。例えば、1000V以上の高耐圧を得ようとすると、5μmより厚い埋め込み酸化膜と、50μmより厚いSOI層が必要である。しかしながら、SOI層1aの厚さtsは、後工程で形成するトレンチ4の加工技術の制限から、図8(a)に示す20μmが限界厚さとなっている。また、埋め込み酸化膜3の膜厚toxは、貼り合わせによって形成されるSOI基板1のウェハの反り量と原石コストの制限から、4μmが限界膜厚となっている。このため、図8に示す半導体装置9bでは、640Vより大きな耐圧を確保するのは困難である。従って、図8の半導体装置9bと同様の構造を有し、図7の高電圧IC9のレベルシフト回路に適用されたLDMOS9aでは、EV車等で要求される、1200Vの耐圧は確保することができない。
S ソース(電極)
D ドレイン(電極)
G ゲート
1 (SOI)基板
1a SOI層
2 支持基板
3 埋め込み酸化膜
5,5R,5WU,5WL,5TU,5TL,5a 中空溝
5c 角部
6 P導電型領域
7 LOCOS
8 トレンチ
Z 絶縁分離トレンチ
Claims (17)
- 埋め込み酸化膜上にあるSOI層の表層部に、横型MOSトランジスタ(LDMOS)が形成されてなる半導体装置であって、
シリコン(Si)より誘電率の低い低誘電率領域が、前記埋め込み酸化膜に当接して、前記LDMOSのソースとドレインの間で形成されてなることを特徴とする半導体装置。 - 前記低誘電率領域が、前記SOI層の下層部に形成されてなることを特徴とする請求項1に記載の半導体装置。
- 前記低誘電率領域が、複数個に分割されて形成されてなることを特徴とする請求項2に記載の半導体装置。
- 前記複数の低誘電率領域が、前記SOI層の厚さ方向で、等しい厚さに形成されてなることを特徴とする請求項3に記載の半導体装置。
- 前記複数の低誘電率領域が、前記LDMOSのソースとドレインの幅方向で、等しい幅に形成されてなることを特徴とする請求項3または4に記載の半導体装置。
- 前記複数の低誘電率領域が、前記LDMOSのソースとドレインの幅方向で、等しい間隔で並んで配置されてなることを特徴とする請求項3乃至5のいずれか一項に記載の半導体装置。
- 前記低誘電率領域の角部が、丸められてなることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記LDMOSが、前記埋め込み酸化膜に達する絶縁分離トレンチによって絶縁分離されてなり、
前記低誘電率領域が、前記絶縁分離トレンチにより取り囲まれた領域の全面積を占めるように形成されてなることを特徴とする請求項1または2に記載の半導体装置。 - 前記低誘電率領域が、中空溝であることを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。
- 前記低誘電率領域が、酸化シリコン、カーボン含有酸化シリコン(SiOC)、FSG(SiOF)、フッ素化ポリイミド、CPFPのいずれかの埋め込み溝であることを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。
- 前記SOI層が、N導電型であることを特徴とする請求項1乃至10のいずれか一項に記載の半導体装置。
- 前記SOI層の表層部に、前記LDMOSのソースからドレインに向って、P導電型領域が形成されてなることを特徴とする請求項11に記載の半導体装置。
- 前記半導体装置が、700V以上の耐圧を有することを特徴とする請求項1乃至12のいずれか一項に記載の半導体装置。
- 前記半導体装置が、車載用の半導体装置であり、
インバータ駆動用の高電圧ICにおけるレベルシフト回路に用いられることを特徴とする請求項13に記載の半導体装置。 - 埋め込み酸化膜上にあるSOI層の表層部に、横型MOSトランジスタ(LDMOS)が形成され、
中空溝が、前記埋め込み酸化膜に当接して、前記LDMOSのソースとドレインの間で形成されてなる半導体装置の製造方法であって、
2枚のシリコン基板を準備し、
一方のシリコン基板の表面に、前記中空溝となる溝を形成し、もう一方のシリコン基板の表面に、前記埋め込み酸化膜となる酸化膜を形成し、
前記溝と酸化膜を当接するようにして、2枚のシリコン基板を貼り合わせることを特徴とする半導体装置の製造方法。 - 埋め込み酸化膜上にあるSOI層の表層部に、横型MOSトランジスタ(LDMOS)が形成され、
酸化シリコン、カーボン含有酸化シリコン(SiOC)、FSG(SiOF)、フッ素化ポリイミド、CPFPのいずれかの埋め込み溝が、前記埋め込み酸化膜に当接して、前記LDMOSのソースとドレインの間で形成されてなる半導体装置の製造方法であって、
2枚のシリコン基板を準備し、
一方のシリコン基板の表面に、前記酸化シリコン、カーボン含有酸化シリコン(SiOC)、FSG(SiOF)、フッ素化ポリイミド、CPFPのいずれかの埋め込み溝となる溝を形成して、前記溝内に酸化シリコン、カーボン含有酸化シリコン(SiOC)、FSG(SiOF)、フッ素化ポリイミド、CPFPのいずれかを埋め込み、もう一方のシリコン基板の表面に、前記埋め込み酸化膜となる酸化膜を形成し、
前記酸化シリコン、カーボン含有酸化シリコン(SiOC)、FSG(SiOF)、フッ素化ポリイミド、CPFPのいずれかの埋め込み溝と酸化膜を当接するようにして、2枚のシリコン基板を貼り合わせることを特徴とする半導体装置の製造方法。 - 埋め込み酸化膜上にあるSOI層の表層部に、横型MOSトランジスタ(LDMOS)が形成され、
中空溝が、前記埋め込み酸化膜に当接して、前記LDMOSのソースとドレインの間で形成されてなる半導体装置の製造方法であって、
異方性エッチングにより、前記埋め込み酸化膜上にあるSOI層の表面から垂直にトレンチを形成し、次に、前記トレンチの先端部をサイドエッチングすることにより、前記中空溝を形成することを特徴とする半導体装置の製造方法。
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JP2006142012A JP5017926B2 (ja) | 2005-09-28 | 2006-05-22 | 半導体装置およびその製造方法 |
DE102006045214A DE102006045214B4 (de) | 2005-09-28 | 2006-09-25 | Halbleitervorrichtung mit einem LDMOS-Transistor und Verfahren zur Herstellung derselben |
US11/526,652 US7667267B2 (en) | 2005-09-28 | 2006-09-26 | Semiconductor device having LDMOS transistor and method for manufacturing the same |
US12/654,230 US7799623B2 (en) | 2005-09-28 | 2009-12-15 | Method for manufacturing semiconductor device having LDMOS transistor |
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JP2006142012A JP5017926B2 (ja) | 2005-09-28 | 2006-05-22 | 半導体装置およびその製造方法 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008294407A (ja) * | 2007-04-25 | 2008-12-04 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2012038878A (ja) * | 2010-08-06 | 2012-02-23 | Toyota Central R&D Labs Inc | 半導体装置とその製造方法 |
JP2013232577A (ja) * | 2012-05-01 | 2013-11-14 | Mitsubishi Electric Corp | 半導体装置 |
WO2014041822A1 (ja) * | 2012-09-14 | 2014-03-20 | 独立行政法人産業技術総合研究所 | 半導体基板及び半導体素子 |
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Also Published As
Publication number | Publication date |
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JP5017926B2 (ja) | 2012-09-05 |
US20070069292A1 (en) | 2007-03-29 |
DE102006045214B4 (de) | 2013-08-01 |
US7667267B2 (en) | 2010-02-23 |
DE102006045214A1 (de) | 2007-04-12 |
US7799623B2 (en) | 2010-09-21 |
US20100099225A1 (en) | 2010-04-22 |
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