JP2014517509A - ドリフト領域の下にキャビティを備えるdmosトランジスタ - Google Patents
ドリフト領域の下にキャビティを備えるdmosトランジスタ Download PDFInfo
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- JP2014517509A JP2014517509A JP2014508559A JP2014508559A JP2014517509A JP 2014517509 A JP2014517509 A JP 2014517509A JP 2014508559 A JP2014508559 A JP 2014508559A JP 2014508559 A JP2014508559 A JP 2014508559A JP 2014517509 A JP2014517509 A JP 2014517509A
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- 239000012212 insulator Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 65
- 239000004065 semiconductor Substances 0.000 claims description 49
- 239000013078 crystal Substances 0.000 claims description 38
- 239000002019 doping agent Substances 0.000 claims description 17
- 210000000746 body region Anatomy 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000007943 implant Substances 0.000 description 6
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- -1 oxide Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (15)
- DMOSトランジスタであって、
シリコンオンインシュレータ(SOI)構造を有し、
前記SOI構造が、
上面を有するバルク領域、
前記バルク領域の上面に接し、上面及び底面を有する絶縁層、及び、
前記絶縁層の前記上面に接する単結晶半導体領域、
を有し、
前記単結晶半導体領域が、
前記絶縁層に接する第1の導電型のドープ領域、
前記絶縁層に接する第2の導電型のドリフト領域、及び、
前記絶縁層の前記底面の一部を露出させる、前記バルク領域内のキャビティ、
を有し、
前記絶縁層の前記底面の前記一部が、前記ドリフト領域の直下に位置する、
DMOSトランジスタ。 - 請求項1に記載のDMOSトランジスタであって、
前記単結晶半導体領域が、
前記ドリフト領域に接し且つ前記ドープ領域から離間して位置する前記第2の導電型のドレイン領域、及び、
前記ドープ領域に接し且つ前記ドリフト領域から離間して位置する前記第2の導電型のソース領域、
を更に有し、
前記ドリフト領域及び前記ソース領域の間に水平に位置し且つそれらに接する前記ドープ領域のチャネル領域、
を更に含むDMOSトランジスタ。 - 請求項2に記載のDMOSトランジスタであって、前記ドープ領域が、
前記絶縁層に接するウェル領域、
前記ウェル領域より高いドーパント濃度を有し、前記ウェル領域に接し、前記チャネル領域を含む、ボディ領域、及び、
前記ボディ領域より高いドーパント濃度を有し、前記ボディ領域に接するコンタクト領域、
を含むDMOSトランジスタ。 - 請求項2に記載のDMOSトランジスタであって、
前記チャネル領域に接し、その上に位置する非導電層、及び、
前記非導電層に接し、前記チャネル領域の上に位置するゲート、
を更に含むDMOSトランジスタ。 - 請求項4に記載のDMOSトランジスタであって、前記ドリフト領域が前記絶縁層に接する、DMOSトランジスタ。
- 請求項4に記載のDMOSトランジスタであって、前記ドープ領域が前記ドリフト領域と前記絶縁層との間に垂直に位置する、DMOSトランジスタ。
- 請求項4に記載のDMOSトランジスタであって、前記キャビティが前記ゲートの一部の直下に位置する、DMOSトランジスタ。
- 請求項4に記載のDMOSトランジスタであって、前記キャビティのいかなる部分も、前記ゲートの任意の部分の直下に位置しない、DMOSトランジスタ。
- 請求項8に記載のDMOSトランジスタであって、前記ゲートの最も近くに位置する前記キャビティのエッジが、前記キャビティの最も近くに位置する前記ゲートのエッジに一致して位置する垂直ラインから水平に離間する、DMOSトランジスタ
- DMOSトランジスタを形成する方法であって、
シリコンオンインシュレータ(SOI)構造のバルク領域上で対応する複数の領域を露出させるように、単結晶半導体領域及び絶縁層を介する複数の開口を選択的にエッチングすることであって、前記複数の開口が複数の側壁を有すること、
前記複数の開口の前記複数の側壁に接する複数の側壁スペーサを形成すること、及び、
前記開口の各々の下に位置する単一のキャビティを形成するように、前記複数の開口を介して前記バルク領域をウェットエッチングすること、
を含む方法。 - 請求項10に記載の方法であって、前記複数の開口を塞ぐ複数の非導電プラグを形成することを更に含む方法。
- 請求項10に記載の方法であって、第1の導電型のドープ領域及び第2の導電型のドリフト領域を形成することを更に含み、前記ドープ領域が前記絶縁層に接し、前記ドリフト領域が前記ボディ領域に接する、方法。
- 請求項12に記載の方法であって、前記キャビティが前記ドリフト領域の全ての直下に位置する方法。
- 請求項12に記載の方法であって、前記キャビティが前記ドリフト領域の全てより少ない部分の直下に位置する、方法。
- 請求項12に記載の方法であって、前記第2の導電型のソース及びドレイン領域を形成することを更に含み、前記ソース領域が前記ドープ領域に接し且つ前記ドリフト領域から離間し、前記ドレイン領域が前記ドリフト領域に接し且つ前記ドープ領域から離間する、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/094,645 | 2011-04-26 | ||
US13/094,645 US8524548B2 (en) | 2011-04-26 | 2011-04-26 | DMOS Transistor with a cavity that lies below the drift region |
PCT/US2012/035249 WO2012149184A2 (en) | 2011-04-26 | 2012-04-26 | Dmos transistor with cavity below drift region |
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JP2014517509A true JP2014517509A (ja) | 2014-07-17 |
JP2014517509A5 JP2014517509A5 (ja) | 2015-06-18 |
JP6073862B2 JP6073862B2 (ja) | 2017-02-01 |
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US (1) | US8524548B2 (ja) |
EP (1) | EP2724378B1 (ja) |
JP (1) | JP6073862B2 (ja) |
CN (1) | CN103503151B (ja) |
WO (1) | WO2012149184A2 (ja) |
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US9455339B2 (en) * | 2014-09-09 | 2016-09-27 | Macronix International Co., Ltd. | High voltage device and method for manufacturing the same |
CN105023938B (zh) * | 2015-08-25 | 2018-08-24 | 西华大学 | 一种soi横向功率器件耐压结构及其制备方法 |
US10854455B2 (en) * | 2016-11-21 | 2020-12-01 | Marvell Asia Pte, Ltd. | Methods and apparatus for fabricating IC chips with tilted patterning |
JP2018125518A (ja) * | 2017-02-03 | 2018-08-09 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ、製造方法 |
CN117012835B (zh) * | 2023-10-07 | 2024-01-23 | 粤芯半导体技术股份有限公司 | 横向扩散金属氧化物半导体器件及其制造方法 |
CN117116971A (zh) * | 2023-10-24 | 2023-11-24 | 绍兴中芯集成电路制造股份有限公司 | Soi衬底及其制备方法、晶体管及其制备方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06188438A (ja) * | 1992-10-21 | 1994-07-08 | Mitsubishi Electric Corp | 誘電体分離半導体装置及びその製造方法 |
US6211551B1 (en) * | 1997-06-30 | 2001-04-03 | Matsushita Electric Works, Ltd. | Solid-state relay |
JP2002110987A (ja) * | 2000-09-26 | 2002-04-12 | Matsushita Electric Works Ltd | 半導体装置及びその製造方法 |
JP2003504875A (ja) * | 1999-07-12 | 2003-02-04 | デイヴィーズ、ロバート、ブルース | 受動部品用のモノリシック低誘電率プラットフォームおよび製造方法 |
JP2006173204A (ja) * | 2004-12-13 | 2006-06-29 | Toyota Motor Corp | 半導体装置の製造方法 |
JP2007123823A (ja) * | 2005-09-28 | 2007-05-17 | Denso Corp | 半導体装置およびその製造方法 |
JP2007158139A (ja) * | 2005-12-07 | 2007-06-21 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2008541421A (ja) * | 2005-05-03 | 2008-11-20 | エヌエックスピー ビー ヴィ | 半導体デバイスの製造方法および該製造方法により得られた半導体デバイス |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5389569A (en) * | 1992-03-03 | 1995-02-14 | Motorola, Inc. | Vertical and lateral isolation for a semiconductor device |
EP1113492B9 (en) * | 1999-12-31 | 2010-02-03 | STMicroelectronics S.r.l. | Method for manufacturimg a SOI wafer |
EP1319252B1 (en) | 2000-09-21 | 2012-02-15 | Cambridge Semiconductor Limited | Semiconductor device and method of forming a semiconductor device |
CN1663049A (zh) * | 2002-06-26 | 2005-08-31 | 剑桥半导体有限公司 | 横向半导体器件 |
US7153753B2 (en) | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
GB0411971D0 (en) | 2004-05-28 | 2004-06-30 | Koninkl Philips Electronics Nv | Semiconductor device and method for manufacture |
JP4624084B2 (ja) * | 2004-11-24 | 2011-02-02 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
WO2006109265A1 (en) * | 2005-04-14 | 2006-10-19 | Nxp B.V. | Semiconductor device and method for manufacture |
US7489018B2 (en) * | 2005-04-19 | 2009-02-10 | Kabushiki Kaisha Toshiba | Transistor |
US7602037B2 (en) | 2007-03-28 | 2009-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage semiconductor devices and methods for fabricating the same |
JP2010251344A (ja) * | 2009-04-10 | 2010-11-04 | Hitachi Ltd | 半導体装置およびその製造方法 |
US8482031B2 (en) | 2009-09-09 | 2013-07-09 | Cambridge Semiconductor Limited | Lateral insulated gate bipolar transistors (LIGBTS) |
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2011
- 2011-04-26 US US13/094,645 patent/US8524548B2/en active Active
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2012
- 2012-04-26 EP EP12776943.8A patent/EP2724378B1/en active Active
- 2012-04-26 JP JP2014508559A patent/JP6073862B2/ja active Active
- 2012-04-26 CN CN201280020245.XA patent/CN103503151B/zh active Active
- 2012-04-26 WO PCT/US2012/035249 patent/WO2012149184A2/en unknown
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06188438A (ja) * | 1992-10-21 | 1994-07-08 | Mitsubishi Electric Corp | 誘電体分離半導体装置及びその製造方法 |
US6211551B1 (en) * | 1997-06-30 | 2001-04-03 | Matsushita Electric Works, Ltd. | Solid-state relay |
JP2003504875A (ja) * | 1999-07-12 | 2003-02-04 | デイヴィーズ、ロバート、ブルース | 受動部品用のモノリシック低誘電率プラットフォームおよび製造方法 |
JP2002110987A (ja) * | 2000-09-26 | 2002-04-12 | Matsushita Electric Works Ltd | 半導体装置及びその製造方法 |
JP2006173204A (ja) * | 2004-12-13 | 2006-06-29 | Toyota Motor Corp | 半導体装置の製造方法 |
JP2008541421A (ja) * | 2005-05-03 | 2008-11-20 | エヌエックスピー ビー ヴィ | 半導体デバイスの製造方法および該製造方法により得られた半導体デバイス |
JP2007123823A (ja) * | 2005-09-28 | 2007-05-17 | Denso Corp | 半導体装置およびその製造方法 |
JP2007158139A (ja) * | 2005-12-07 | 2007-06-21 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8524548B2 (en) | 2013-09-03 |
EP2724378B1 (en) | 2020-01-22 |
WO2012149184A3 (en) | 2013-01-10 |
CN103503151B (zh) | 2016-08-24 |
EP2724378A2 (en) | 2014-04-30 |
US20120273881A1 (en) | 2012-11-01 |
EP2724378A4 (en) | 2015-07-29 |
CN103503151A (zh) | 2014-01-08 |
WO2012149184A2 (en) | 2012-11-01 |
JP6073862B2 (ja) | 2017-02-01 |
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