CN105023938B - 一种soi横向功率器件耐压结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种SOI横向功率器件耐压结构，包括衬底层、埋氧层、有源层，埋氧层设置于衬底层与有源层之间，在埋氧层和衬底层之间设有浓度从源到漏减小的P型掺杂层。本发明所公开的耐压结构有效提高器件动态耐压，降低比导通电阻和开关功耗以及器件工作温度，在高压、高频智能功率集成电路等领域具有广泛的适用性。
Description
技术领域
本发明涉及一种半导体功率器件，特别涉及一种横向SOI耐压功率器件。
背景技术
SOI横向功率器件具有高速、低功耗、抗辐照等优点，在智能功率集成电路中得以广泛应用。但较低的纵向耐压，限制了其在高压功率集成电路领域的应用。
针对上述问题，本领域提供了诸多解决方案，其核心思路是基于下述物理学发现：硅厚度小于0.5微米时，硅的纵向临界击穿电场会随硅厚度减小而迅速增加。利用这一原理，超薄SOI器件结合漂移区线性变掺杂技术能大大提高器件静态耐压。此类解决方案的缺点在于靠近源端的漂移区掺杂浓度过低，导致比导通电阻过大，而且如果按动态耐压优化掺杂浓度，还会进一步增加比导通电阻。已有的工艺实现证明，这种改进方案在器件处于开态时，靠近源端的高阻会引起高温，使器件的性能、可靠性降低；并且整个工艺成本很高，难于加工生产。
针对上述问题，本领域还提出过另一类解决方案，是利用深耗尽效应提高动态耐压，从而改善SOI功率器件在开关状态下的可靠性。但此种技术方案在使用中显示对纵向耐压有明显提高，但对横向耐压没有提高。
发明内容
针对现有技术的不足，本发明公开了一种SOI横向功率器件耐压结构，通过在埋氧层与衬底之间引入阶梯或线性变掺杂P型层，显著改善了SOI横向功率器件的动态耐压，降低功率器件的比导通电阻、开关功耗和工作温度，实现了耐压与比导通电阻的良好平衡，适合于高压、高频智能功率集成电路等需要高可靠性的应用环境。
具体地说，本发明是通过如下技术方案实现的：
一种SOI横向功率器件耐压结构，包括衬底层、埋氧层、有源层，埋氧层设置于衬底层与有源层之间，在埋氧层和衬底层之间设有浓度从源到漏减小的P型掺杂层(以下简称变掺杂层)。
通过使用浓度渐变的衬底变掺杂层。当SOI横向功率器件工作在开关状态下，衬底变掺杂层将对漂移区电场调制，使器件横向表面电场均匀分布。使得漂移区可采用高均匀掺杂，同时能获得耐压与比导通电阻的平衡。
其中，掺杂层的厚度为0.5-1um，浓度变化范围为2×1017-4×1014cm-3之间，上述的参数可以根据需要调整。
本发明的耐压结构可以广泛适用于各种横向功率器件，例如基于SOI技术的IGBT、PiN二极管、LDMOS等，优选埋氧层为SiO2介质，衬底层为P型衬底，掺杂层为P型衬底变掺杂层。
在本发明中，所用的有源层可以是各种有源半导体层，包括但不限于Si、SiC等半导体材料。
作为本发明的一种具体工艺实现，本发明的耐压结构，在有源层上还设有n+漏区、n+源区、p阱、n-漂移区，n+漏区上方为漏电极，p阱和n-漂移区上方为栅氧化层，栅氧化层上方为栅电极，n+源区上方为源电极，衬底变掺杂层自n+源区到n+漏区方向浓度依次降低。
上述的浓度变化方式并不受到特别限定。根据动态耐压需求，可将其处理为阶梯变掺杂或线性变掺杂。当对动态耐压要求较低时，阶梯掺杂分区数较少，工艺实现容易；当对动态耐压要求较高时，增加分区数目至其线性分布。通常的，如果漂移区长度不变，如50um，分区数大于100可视为是线性变掺杂，此时器件能获得最高动态耐压。
相应的，本发明还公开了所述SOI横向功率器件耐压结构的制备方法，包括在衬底层上，分区进行离子注入，形成一层掺杂层的步骤，其余工艺采用常规SOI器件加工工艺即可。
附图说明
图1为本发明的SOI横向功率器件耐压结构剖面示意图；
图2为采用本发明结构的SOI横向功率器件等势线分布图。
具体实施方式
在如下实施中，申请人结合附图对本发明的具体实现进行了详细描述，如下所提供的实施仅为示意性的，并不对本发明构成特别限制。本领域的技术人员在不脱离本发明的精神和范围基础上可以对本发明进行各种改动和变型，依旧属于本发明的保护范围。
参考图1，本发明的SOI横向功率器件耐压结构，包括衬底1、埋氧层2、有源层3，埋氧层2位于衬底层1与有源层3之间，在埋氧层2与衬底1之间具有浓度单向渐变的掺杂层4。
其中，埋氧层为SiO2介质，衬底为P型衬底，掺杂层为P型衬底变掺杂层。
其中，有源层上设有n+漏区、n+源区、p阱、n-漂移区，n+漏区上方为漏电极，p阱和n-漂移区上方为栅氧化层，栅氧化层上方为栅电极，n+源区上方为源电极，变掺杂层自n+源区到n+漏区方向浓度依次降低，即从1区到n区方向浓度逐渐降低；在P型衬底下方为衬底电极。
参考图2，显示了本发明的功率器件在开关状态下的等势线分布。当器件由开态转为关态，漏压迅速升高，埋氧层下面电子反型层来不及形成，因此在衬底中形成深耗尽层。
与此同时，衬底变掺杂层被耗尽，形成了不同浓度的负电荷区。这些不同负电荷区域对漂移区中的横向电场进行调制，有效地提高了横向耐压，而漂移区可以采用高浓度的均匀掺杂。
在纵向上，由于SOI硅层很薄，硅的临界击穿电场被大大提高，加上衬底深耗尽层也能承受漏压，因此纵向耐压也大大提高。从图2的器件二维等势线分布图可以看出，器件横向表面等势线分布均匀。从纵向看，埋氧层中等势线很密，衬底中也有很多等势线分布，表明了埋氧层、衬底都承担了当然多的漏电压，故而器件能获得很高的耐压。
申请人进行的研究显示，在多种结构参数下，如漂移区长度40um，漂移区厚度0.2um，埋氧层厚度1um，衬底厚度大于30um时，动态耐压可达600V以上，比常规结构高出约6倍。由于衬底变掺杂层对漂移区横向电场的调制，使得漂移区掺杂浓度增加，有效地降低了器件的比导通电阻和温度。
Claims (6)
1.一种SOI横向功率器件耐压结构，用于改善SOI横向功率器件的动态耐压，其特征在于包括衬底层、埋氧层、有源层，埋氧层设置于衬底层与有源层之间，在埋氧层和衬底层之间设有浓度从源到漏减小的P型掺杂层，在源漏之间的漂移区采用均匀掺杂。
2.根据权利要求1所述的耐压结构，其特征在于P型掺杂层的厚度为0.5‐1um，P型掺杂层浓度变化范围为2×1017‐4×1014cm‐3之间。
3.根据权利要求1所述的耐压结构，其特征在于埋氧层为SiO2介质，衬底层为P型硅衬底，P型掺杂层为P型硅衬底变掺杂层。
4.根据权利要求1所述的耐压结构，其特征在于有源层为硅材料。
5.根据权利要求1所述的耐压结构，其特征在于还设置有n+漏区、n+源区、p阱、n‐漂移区，n+漏区上方为漏电极，p阱和n‐漂移区上方为栅氧化层，栅氧化层上方为栅电极，n+源区上方为源电极，P型掺杂层自n+源区到n+漏区方向浓度依次降低。
6.权利要求1所述的SOI横向功率器件耐压结构的制备方法，其特征在于包括在衬底层上，分区进行离子注入，形成一层P型掺杂层的步骤。
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