CN110212017B - 一种具有阻性场板的超结带槽横向耐压区 - Google Patents
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Abstract
本发明属于半导体功率器件领域，涉及横向耐压区，具体提供一种有阻性场板的超结带槽横向耐压区，应用于半导体功率器件的结边缘终端或者横向半导体功率器件包括LDMOS(Lateral Double‑Diffused MOSFET)、LIGBT(Lateral Insulated Gate Bipolar Transistor)。本发明通过在超结带槽横向耐压区中的绝缘介质槽与具有超结结构的半导体漂移区之间增加阻性场板，调制反向耐压状态下的表面电场分布，使其更加均匀，从而优化击穿电压与比导通电阻之间的关系。
Description
技术领域
本发明属于半导体功率器件领域，涉及横向耐压区，特别是带有槽型结构的横向耐压区；可应用于半导体功率器件的结边缘终端，或者横向半导体功率器件包括LDMOS(Lateral Do uble-Diffused MOSFET)、LIGBT(Lateral Insulated Gate BipolarTransistor)等的耐压区。
背景技术
横向半导体功率器件，如LDMOS(Lateral Double-Diffused MOSFET，LDMOS)等，在功率集成电路上有着广泛的应用，但它们通常需要很长的横向耐压区来承受高的反向耐压，占用芯片面积很大。为此人们提出了一种带有槽型结构的横向耐压区(本文称为“普通的带槽横向耐压区”)，如图1所示；该耐压区通过在表面嵌入一个填充绝缘介质的槽，来代替原有的半导体材料，以获得两个主要优点：其一、因为绝缘介质的临界击穿场强一般远高于半导体材料的，所以与以前的无槽耐压区相比，在承受相同反向电压的条件下，有槽耐压区所需的横向宽度更小；其二、所嵌入的介质槽等效增加了半导体中漂移区的总长度，从无槽时的O1至O4的直线距离，增加为带槽时的O1-O2-O3-O4这一折叠的距离(漂移区折叠总长)，利于在相同横向器件宽度的条件下获得更高的击穿电压。
进一步地，把“超结技术”(美国专利：US 5216275A)应用到普通的带槽横向耐压区中，可以延伸出一种有超结漂移区的带槽横向耐压区(本文称为“传统的超结带槽横向耐压区”)，如图2所示；这种结构的优点在于，P型漂移区08可以对N型漂移区02进行电荷补偿，两者形成超结漂移区，从而在相同耐压要求下提高漂移区浓度，降低漂移区电阻。
然而无论是普通的带槽横向耐压区，还是传统的超结带槽横向耐压区，都存在一个致命弱点：它们的表面电场分布会受到槽电容的破坏。这里所谓的槽电容，其介质就是槽中的绝缘介质，其两个极板分别就是O1-O2左侧的和O3-O4右侧的半导体区。当耐压区反向耐压时，阴极07接高电位，阳极05接低电位，在槽电容上会形成一个纵向变化的电势差；具体而言，在槽的表面，这个电势差是O1与O4之间的电压，接近阴极与阳极之间所承受的反向电压；在槽的底部，这个电势差是O2与O3之间的电压，接近于零；槽电容上纵向变化的电势差会在两个极板感应出数量也相应纵向变化的电荷，这些电荷将破坏耐压区的表面电场分布；特别地，对于传统的超结带槽横向耐压区而言，这些电荷破坏了P型漂移区08和N型漂移区02之间的电荷平衡条件，使超结技术的优势不能完全发挥出来。
发明内容
本发明之目的在于提出一种有阻性场板的超结带槽横向耐压区，用以优化击穿电压与比导通电阻之间的关系。本发明在传统的超结带槽横向耐压区的基础上，在槽内嵌入一个阻性场板，它的两端分别与阴极和阳极相连，阻性场板具有很高、且均匀的电阻率。当耐压区反向耐压时，阻性场板中将流过一股微弱的电流，在电流的路径上将产生均匀的电势分布；如此可以对半导体中的表面电场分布起到调制作用，尤其屏蔽了槽电容的影响，缩短槽的宽度，使超结漂移区满足电荷平衡条件，最终优化击穿电压与比导通电阻之间的关系。
为实现上述目的，本发明采用的技术方案为：
一种具有阻性场板的超结带槽横向耐压区，包括：衬底01、N型漂移区02、绝缘介质槽03、P+阳极区04、阳极05、N+阴极区06、阴极07、P形漂移区08及阻性场板09；其中，所述N型漂移区02设置于衬底01上，所述P形漂移区08设置于N型漂移区02中，所述绝缘介质槽03设置于P形漂移区08中，所述P+阳极区04与N+阴极区06分别设置于绝缘介质槽03两侧、且均位于N型漂移区02与P形漂移区08的上方，所述阳极05设置于P+阳极区04上，所述阴极07设置于N+阴极区06上；其特征在于，所述绝缘介质槽03与P形漂移区08之间设置所述阻性场板09，且阻性场板09与阳极05、阴极07均相连。
进一步地，所述阻性场板09与P型漂移区之间还设置有一层绝缘介质缓冲层10。
更进一步地，所述阻性场板(09)的制作材料为semi-insulating poly-silicon(SIPOS)。
所述绝缘介质槽03中填充介质为临界电场强度高于常用半导体材料例如硅、砷化镓、磷化铟、碳化硅、氮化镓等的绝缘介质材料，包括SiO2、Si3N4、BPSG、BenzoCycloButene(BCB)或者PolyTetraFluoroEthylene(PTFE)。
所述衬底01采用硅半导体衬底或者silicon-on-insulator(SOI)材料。
本发明的有益效果在于：
本发明提供一种有阻性场板的超结带槽横向耐压区。阻性场板具有高的电阻率、良好的均匀性，其两端分别与阴极和阳极相连。当耐压区承受反向电压时，阻性场板中同时也将流过一股微弱的电流，随之产生均匀的电势分布。这可以对耐压区的表面电场起到调制作用，屏蔽了以槽中绝缘介质为介质、以两侧漂移区为极板的槽电容的影响，使得器件宽度可以尽量缩小，使得超结漂移区可以达到电荷平衡条件，优化击穿电压与比导通电阻之间的关系。
附图说明
图1为普通的带槽横向耐压区结构示意图。
图2为传统的超结带槽横向耐压区结构示意图，其中，P型漂移区08与N型漂移区02形成超结漂移区。
图3为本发明实施例1中有阻性场板的超结带槽横向耐压区结构示意图，其中，09为阻性场板。
图4为一种应用了普通的带槽横向耐压区的N沟道LDMOS的结构示意图。
图5为一种应用了传统的超结带槽横向耐压区的N沟道LDMOS的结构示意图。
图6为一种应用了本发明实施例1中有阻性场板的超结带槽横向耐压区的N沟道LDMOS的结构示意图。
图7为反向漏电流密度随承受电压变化的曲线对比图。
图8为临界击穿状态下表面电势分布的对比图，等电势线之间的最小间隔均为20V。
图9为临界击穿状态下表面电场分布的对比图，此图表示沿槽边缘的电场分布，其中，横坐标做了归一化处理，横坐标表示沿槽边缘离开O1点的距离除以漂移区折叠总长。
图10为一种电路偏置下正向电压电流特性的对比图。
图11为另一种电路偏置下正向电压电流特性的对比图。
图12为本发明实施例2中有阻性场板的超结带槽横向耐压区结构示意图，其中，10为绝缘介质缓冲层。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
实施例1
本实施例提供一种具有阻性场板的超结带槽横向耐压区，其结构如图3所示；包括：衬底01、N型漂移区02、绝缘介质槽03、P+阳极区04、阳极05、N+阴极区06、阴极07、P形漂移区08及阻性场板09；其中，所述N型漂移区02设置于衬底01上，所述P形漂移区08设置于N型漂移区02中，所述绝缘介质槽03设置于P形漂移区08中，所述P+阳极区04与N+阴极区06分别设置于绝缘介质槽03两侧、且均位于N型漂移区02与P形漂移区08的上方，所述阳极05设置于P+阳极区04上，所述阴极07设置于N+阴极区06上；所述绝缘介质槽03与P形漂移区08之间设置所述阻性场板09，且阻性场板09与阳极05、阴极07均相连。
上述耐压区的工作原理为：当耐压区承受反向电压时，所设置的高阻均匀的阻性场板上会有一股微弱的电流从阴极流向阳极；这股电流在阻性场板上产生均匀分布的电势变化，可以调制耐压区表面的电场分布，使其尽可能平坦；这样一来有利于在相同耐压要求下缩小槽的宽度以及深度，减小比导通电阻，或是有利于在相同比导通电阻要求下提高耐压；同时，阻性场板与围绕它的P型漂移区电势分布接近，避免了P型漂移区受槽电容的影响而积累感应电荷，于是P型漂移区可与N型漂移区满足超结结构的电荷平衡条件，进一步优化击穿电压与比导通电阻之间的关系。
本实施例中，将上述具有阻性场板的超结带槽横向耐压区应用于N沟道LDMOS器件中，其结构如图6所示，该结构采用了槽栅和SOI衬底；同时，设计了如图4、图5所示的N沟道LDMOS器件作为对比，其中，如图4所示为将如图1所示的普通的带槽横向耐压区应用于N沟道LDMOS器件结构，如图5所示为将如图2所示的传统的超结带槽横向耐压区应用于N沟道LDMOS器件结构。
从工艺上而言，图5对比图4，需增加一步形成P型漂移区的工艺，可以用热扩散、离子注入等方式实现；图6对比图5，需增加一步形成阻性场板的工艺，可以在刻蚀出槽以后，用先淀积高阻材料SIPOS再填充槽介质等方式实现；因而，与图4、图5的之前技术相比，本实施例无需增加过多的操作，并未造成复杂的工艺变化。
对上述三个器件均以“耐压不低于500V”且“比导通电阻尽可能低”为目标进行了仿真优化，优化后得到的器件参数如下表所示：
经过MEDICI软件仿真优化后的500V器件的主要尺寸及掺杂浓度参数
仿真所用的软件为MEDICI；阻性场板在仿真中被定义为厚度为200纳米、电阻率为1×109Ω·cm的SIPOS层；漂移区及衬底中的半导体材料均设为硅。
如图8所示对比了它们的反向电压电流特性，可见，优化后三种器件的击穿电压都大于500V，符合要求；图8同时也给出了本发明器件中流经阻性场板的漏电流密度，虽然在器件击穿以前它几乎充当了整个器件的反向漏电流，但量级只有10-13A/μm，与另两个器件的反向漏电流密度的量级相当，不会构成显著增大的关断状态下的功率损耗。同时，可以预见，如果阻性场板的电阻率增加，其上的漏电流密度会减小，但同时调制作用也减弱；反之如果电阻率减小，调制作用会加强但漏电流密度增加。因此选择合适的电阻率很重要；常见SIPOS层的电阻率一般在1×108Ω·cm至1×1010Ω·cm之间，本实施例中仿真所用的1×109Ω·cm是实际合理的。
如图9和图10所示分别提取了三个器件在临界击穿状态下的表面电势分布和表面电场分布；对比可见，本发明器件的各种电分布要优于另外两个器件，从电势分布上更加均匀，从沿槽的电场分布上更加平坦。仿真结果很好地印证了阻性场板调制优化电场分布的作用，意味着在同样耐压需求下，本发明器件的漂移区折叠总长和槽宽度可以缩减，或是同样漂移区折叠总长和槽宽度下，耐压可以提高。
如图11和图12所示分别提取了不同电路设置下三个器件的正向电压电流特性，在图11中，可观察到虽然它们有相近的阈值电压，但是当器件开启以后，在相同栅压及漏源电压条件下，本发明器件的导通电流密度要显著高于其它两个器件；从图12中进一步可见，当三个器件均处于栅压为10V的正常工作状态时，在同样漏源电压条件下，本发明器件的导通电流密度要显著高于其它两个器件。
最终仿真结果为：应用了普通的带槽横向耐压区的LDMOS，当其击穿电压为500V时，比导通电阻最低值为439mΩ·cm2；应用了传统的超结带槽横向耐压区的LDMOS，当其击穿电压为501V，比导通电阻最低值下降至46mΩ·cm2；应用了本发明的有阻性场板的超结带槽横向耐压区的LDMOS，当其击穿电压为528V时，比导通电阻最低值进一步下降至仅为9mΩ·cm2；可见，本发明器件获得了更优的击穿电压与比导通电阻之间的关系。
实施例2
本实施例提供另一种具有阻性场板的超结带槽横向耐压区，其结构如图12所示；其与实施例1的区别在于：所述阻性场板09与P型漂移区之间还设置有一层绝缘介质缓冲层10；所述绝缘介质缓冲层10可以采用与绝缘介质槽(03)中填充介质相同介质材料，也可以是另外的介质材料，目的是为阻性场板的实施起到缓冲保护的作用。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。
Claims (3)
1.一种具有阻性场板的超结带槽横向耐压区，包括：衬底（01）、N型漂移区（02）、绝缘介质槽（03）、P+阳极区（04）、阳极（05）、N+阴极区（06）、阴极（07）、P型漂移区（08）及阻性场板（09）；其中，所述N型漂移区（02）设置于衬底（01）上，所述P型漂移区（08）设置于N型漂移区（02）中，所述绝缘介质槽（03）设置于P型漂移区（08）中，所述P+阳极区（04）与N+阴极区（06）分别设置于绝缘介质槽（03）两侧、且均位于N型漂移区（02）与P型漂移区（08）的上方，所述P+阳极区（04）、N+阴极区（06）均与N型漂移区（02）、P型漂移区（08）相接触，所述阳极（05）设置于P+阳极区（04）上，所述阴极（07）设置于N+阴极区（06）上；其特征在于，所述绝缘介质槽（03）与P型漂移区（08）之间设置所述阻性场板（09），且阻性场板（09）与阳极（05）、阴极（07）均相连。
2.按权利要求1所述具有阻性场板的超结带槽横向耐压区，其特征在于，所述阻性场板（09）与P型漂移区（08）之间还设置有一层绝缘介质缓冲层（10）。
3.按权利要求1或2所述具有阻性场板的超结带槽横向耐压区，其特征在于，阻性场板（09）的制作材料为半绝缘多晶硅（SIPOS）。
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