JP2007122834A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP2007122834A JP2007122834A JP2005316463A JP2005316463A JP2007122834A JP 2007122834 A JP2007122834 A JP 2007122834A JP 2005316463 A JP2005316463 A JP 2005316463A JP 2005316463 A JP2005316463 A JP 2005316463A JP 2007122834 A JP2007122834 A JP 2007122834A
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- JP
- Japan
- Prior art keywords
- sense amplifier
- bit line
- twisted
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Abstract
【解決手段】 本発明の半導体記憶装置のセンスアンプは、左右のトランスファーゲート間のほぼ中央位置にあるセンスアンプ内で、ビット線対をツイストさせる。1組おきのビット線対をツイストさせることで、隣接カップリングノイズが相殺される。このようにレイアウト面積の増大を伴うことなく、ビット線対をツイストさせ、センスアンプ内の隣接カップリングノイズの影響を受けなくすることができる高速、安定動作するセンスアンプ、及びこのセンスアンプを備えた半導体記憶装置が得られる。
【選択図】 図8
Description
TG―L,TG−R トランスファーゲート
MA―L,MA−R メモリセルアレイ
D,DB ビット線
A,B,D,E ビット線(センスアンプ内部)
Pre−L,Pre−R プリチャージ回路
PRE プリチャージ信号
HVC プリチャージ電位
SAP、SAN 電源
YSW I/Oバスとの選択的接続スイッチ
K 配線層
Claims (10)
- 半導体記憶装置において、シェアード型センスアンプを備え、前記シェアード型センスアンプの両側にメモリセル部とトランスファーゲートをそれぞれ備え、前記両側のトランスファーゲート間のほぼ中央位置において、ビット線対をツイストしていることを特徴とする半導体記憶装置。
- 前記トランスファーゲートはクロッキングを行い、前記シェアード型センスアンプ部のみ増幅することを特徴とする請求項1に記載の半導体記憶装置。
- 前記シェアード型センスアンプとして、ビット線をツイストしたシェアード型センスアンプと、ビット線をツイストしていないシェアード型センスアンプとを交互に配置したことを特徴とする請求項1に記載の半導体記憶装置。
- 前記ビット線対をリング状に形成された前記シェアード型センスアンプ部のトランジスタのゲート電極によりツイストしていることを特徴とする請求項1に記載の半導体記憶装置。
- 前記ゲート電極の一部を配線として使用していることを特徴とする請求項4に記載の半導体記憶装置。
- 前記ビット線対を前記シェアード型センスアンプ部のウェル分離領域に設けた配線層によりツイストしていることを特徴とする請求項1に記載の半導体記憶装置。
- シェアード型センスアンプにおいて、該シェアード型センスアンプの両側にメモリセル部とトランスファーゲートをそれぞれ備え、前記両側のトランスファーゲート間のほぼ中央となる位置において、ビット線対をツイストしていることを特徴とするシェアード型センスアンプ。
- 前記ビット線対をリング状のトランジスタのゲート電極によりツイストしていることを特徴とする請求項7に記載のシェアード型センスアンプ。
- 前記ゲート電極の一部を配線として使用していることを特徴とする請求項8に記載のシェアード型センスアンプ。
- 前記ビット線対をウェル分離領域に設けた配線層によりツイストしていることを特徴とする請求項7に記載のシェアード型センスアンプ。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005316463A JP4781783B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体記憶装置 |
DE102006051154A DE102006051154A1 (de) | 2005-10-31 | 2006-10-30 | Halbleiterspeichervorrichtung |
US11/589,708 US7423924B2 (en) | 2005-10-31 | 2006-10-31 | Semiconductor memory device |
TW095140151A TW200729458A (en) | 2005-10-31 | 2006-10-31 | Semiconductor memory device |
KR1020060106475A KR100853335B1 (ko) | 2005-10-31 | 2006-10-31 | 반도체 메모리 장치 및 공유 감지 증폭기부 |
CN2006101429217A CN1959837B (zh) | 2005-10-31 | 2006-10-31 | 半导体存储器件 |
US12/183,666 US8022484B2 (en) | 2005-10-31 | 2008-07-31 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005316463A JP4781783B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007122834A true JP2007122834A (ja) | 2007-05-17 |
JP4781783B2 JP4781783B2 (ja) | 2011-09-28 |
Family
ID=37989701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005316463A Expired - Fee Related JP4781783B2 (ja) | 2005-10-31 | 2005-10-31 | 半導体記憶装置 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7423924B2 (ja) |
JP (1) | JP4781783B2 (ja) |
KR (1) | KR100853335B1 (ja) |
CN (1) | CN1959837B (ja) |
DE (1) | DE102006051154A1 (ja) |
TW (1) | TW200729458A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7842976B2 (en) | 2007-10-30 | 2010-11-30 | Elpida Memory, Inc. | Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer |
JP2017120940A (ja) * | 2017-04-11 | 2017-07-06 | ルネサスエレクトロニクス株式会社 | 半導体メモリ |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100909638B1 (ko) * | 2008-06-05 | 2009-07-27 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR101857729B1 (ko) * | 2011-06-17 | 2018-06-20 | 삼성전자주식회사 | 반도체 장치 |
US9941238B2 (en) * | 2015-11-09 | 2018-04-10 | Micron Technology, Inc. | Wiring with external terminal |
US9761312B1 (en) | 2016-03-16 | 2017-09-12 | Micron Technology, Inc. | FeRAM-DRAM hybrid memory |
JP7160894B2 (ja) * | 2018-02-23 | 2022-10-25 | 株式会社半導体エネルギー研究所 | 記憶装置 |
KR20220059749A (ko) | 2020-11-03 | 2022-05-10 | 삼성전자주식회사 | 센싱앰프 및 상기 센싱앰프를 포함하는 반도체 메모리 장치 |
Citations (8)
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JPS63241788A (ja) * | 1987-03-27 | 1988-10-07 | Mitsubishi Electric Corp | ダイナミツク型半導体記憶装置 |
JPS6476494A (en) * | 1987-09-18 | 1989-03-22 | Hitachi Ltd | Semiconductor memory |
JPH0258791A (ja) * | 1988-08-23 | 1990-02-27 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
JPH02181964A (ja) * | 1989-01-09 | 1990-07-16 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH03171492A (ja) * | 1989-11-30 | 1991-07-24 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JP2000123574A (ja) * | 1998-10-19 | 2000-04-28 | Nec Corp | 半導体記憶装置 |
JP2000231790A (ja) * | 1999-02-08 | 2000-08-22 | Hitachi Ltd | 半導体装置 |
JP2003068880A (ja) * | 2001-08-29 | 2003-03-07 | Hitachi Ltd | 半導体集積回路装置 |
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JPH0758587B2 (ja) | 1986-12-11 | 1995-06-21 | 三菱電機株式会社 | 半導体記憶装置 |
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JPH0775116B2 (ja) | 1988-12-20 | 1995-08-09 | 三菱電機株式会社 | 半導体記憶装置 |
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JP2746730B2 (ja) | 1990-05-17 | 1998-05-06 | 富士通株式会社 | 半導体記憶装置 |
KR940008208B1 (ko) * | 1990-12-22 | 1994-09-08 | 삼성전자주식회사 | 반도체 메모리장치의 리던던트 장치 및 방법 |
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EP0758127B1 (en) * | 1995-06-13 | 2001-09-26 | Samsung Electronics Co., Ltd. | Sense amplifier circuit of a nonvolatile semiconductor memory device |
KR100207551B1 (ko) | 1996-07-15 | 1999-07-15 | 윤종용 | 더미 패턴을 갖는 반도체 메모리 장치 |
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JP4632287B2 (ja) | 2003-10-06 | 2011-02-16 | 株式会社日立製作所 | 半導体集積回路装置 |
-
2005
- 2005-10-31 JP JP2005316463A patent/JP4781783B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-30 DE DE102006051154A patent/DE102006051154A1/de not_active Withdrawn
- 2006-10-31 TW TW095140151A patent/TW200729458A/zh unknown
- 2006-10-31 CN CN2006101429217A patent/CN1959837B/zh not_active Expired - Fee Related
- 2006-10-31 US US11/589,708 patent/US7423924B2/en not_active Expired - Fee Related
- 2006-10-31 KR KR1020060106475A patent/KR100853335B1/ko not_active IP Right Cessation
-
2008
- 2008-07-31 US US12/183,666 patent/US8022484B2/en not_active Expired - Fee Related
Patent Citations (8)
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JPS63241788A (ja) * | 1987-03-27 | 1988-10-07 | Mitsubishi Electric Corp | ダイナミツク型半導体記憶装置 |
JPS6476494A (en) * | 1987-09-18 | 1989-03-22 | Hitachi Ltd | Semiconductor memory |
JPH0258791A (ja) * | 1988-08-23 | 1990-02-27 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
JPH02181964A (ja) * | 1989-01-09 | 1990-07-16 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH03171492A (ja) * | 1989-11-30 | 1991-07-24 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JP2000123574A (ja) * | 1998-10-19 | 2000-04-28 | Nec Corp | 半導体記憶装置 |
JP2000231790A (ja) * | 1999-02-08 | 2000-08-22 | Hitachi Ltd | 半導体装置 |
JP2003068880A (ja) * | 2001-08-29 | 2003-03-07 | Hitachi Ltd | 半導体集積回路装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7842976B2 (en) | 2007-10-30 | 2010-11-30 | Elpida Memory, Inc. | Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer |
JP2017120940A (ja) * | 2017-04-11 | 2017-07-06 | ルネサスエレクトロニクス株式会社 | 半導体メモリ |
Also Published As
Publication number | Publication date |
---|---|
US20080290373A1 (en) | 2008-11-27 |
US8022484B2 (en) | 2011-09-20 |
CN1959837A (zh) | 2007-05-09 |
US20070253267A1 (en) | 2007-11-01 |
KR100853335B1 (ko) | 2008-08-21 |
DE102006051154A1 (de) | 2007-05-24 |
CN1959837B (zh) | 2010-06-09 |
US7423924B2 (en) | 2008-09-09 |
KR20070046762A (ko) | 2007-05-03 |
TW200729458A (en) | 2007-08-01 |
JP4781783B2 (ja) | 2011-09-28 |
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