TW200729458A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
TW200729458A
TW200729458A TW095140151A TW95140151A TW200729458A TW 200729458 A TW200729458 A TW 200729458A TW 095140151 A TW095140151 A TW 095140151A TW 95140151 A TW95140151 A TW 95140151A TW 200729458 A TW200729458 A TW 200729458A
Authority
TW
Taiwan
Prior art keywords
pair
sense amplifier
amplifier portion
shared sense
memory device
Prior art date
Application number
TW095140151A
Other languages
English (en)
Inventor
Tomoko Nobutoki
Ken Ota
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of TW200729458A publication Critical patent/TW200729458A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
TW095140151A 2005-10-31 2006-10-31 Semiconductor memory device TW200729458A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005316463A JP4781783B2 (ja) 2005-10-31 2005-10-31 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW200729458A true TW200729458A (en) 2007-08-01

Family

ID=37989701

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095140151A TW200729458A (en) 2005-10-31 2006-10-31 Semiconductor memory device

Country Status (6)

Country Link
US (2) US7423924B2 (zh)
JP (1) JP4781783B2 (zh)
KR (1) KR100853335B1 (zh)
CN (1) CN1959837B (zh)
DE (1) DE102006051154A1 (zh)
TW (1) TW200729458A (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5571871B2 (ja) 2007-10-30 2014-08-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR100909638B1 (ko) * 2008-06-05 2009-07-27 주식회사 하이닉스반도체 반도체 메모리 장치
KR101857729B1 (ko) * 2011-06-17 2018-06-20 삼성전자주식회사 반도체 장치
US9941238B2 (en) * 2015-11-09 2018-04-10 Micron Technology, Inc. Wiring with external terminal
US9761312B1 (en) * 2016-03-16 2017-09-12 Micron Technology, Inc. FeRAM-DRAM hybrid memory
JP6373441B2 (ja) * 2017-04-11 2018-08-15 ルネサスエレクトロニクス株式会社 半導体メモリ
US11423975B2 (en) * 2018-02-23 2022-08-23 Semiconductor Energy Laboratory Co., Ltd. Memory device and method of operating the same
KR20220059749A (ko) 2020-11-03 2022-05-10 삼성전자주식회사 센싱앰프 및 상기 센싱앰프를 포함하는 반도체 메모리 장치
US11984188B2 (en) * 2022-04-29 2024-05-14 Micron Technology, Inc. Semiconductor device having sense amplifier

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JPH0758587B2 (ja) 1986-12-11 1995-06-21 三菱電機株式会社 半導体記憶装置
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JPH0258791A (ja) * 1988-08-23 1990-02-27 Oki Electric Ind Co Ltd 半導体記憶装置
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JPH0775116B2 (ja) 1988-12-20 1995-08-09 三菱電機株式会社 半導体記憶装置
US5010524A (en) * 1989-04-20 1991-04-23 International Business Machines Corporation Crosstalk-shielded-bit-line dram
JP2845526B2 (ja) * 1989-11-30 1999-01-13 株式会社東芝 ダイナミック型半導体記憶装置
JP2746730B2 (ja) 1990-05-17 1998-05-06 富士通株式会社 半導体記憶装置
KR940008208B1 (ko) * 1990-12-22 1994-09-08 삼성전자주식회사 반도체 메모리장치의 리던던트 장치 및 방법
KR950008671A (ko) 1993-09-18 1995-04-19 최영오 신규한 미용비누 조성물 및 그를 이용한 미용비누의 제조방법
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JP3661162B2 (ja) * 1995-06-13 2005-06-15 三星電子株式会社 不揮発性半導体メモリ装置のセンスアンプ
KR100207551B1 (ko) 1996-07-15 1999-07-15 윤종용 더미 패턴을 갖는 반도체 메모리 장치
EP0845815A3 (en) * 1996-11-28 1999-03-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of designing the same and semiconductor integrated circuit device
JP3244039B2 (ja) 1997-11-19 2002-01-07 日本電気株式会社 多値のダイナミック型半導体記憶装置
JP2000123574A (ja) * 1998-10-19 2000-04-28 Nec Corp 半導体記憶装置
JP2000231790A (ja) * 1999-02-08 2000-08-22 Hitachi Ltd 半導体装置
KR100395877B1 (ko) 2000-11-10 2003-08-25 삼성전자주식회사 반도체 메모리의 데이타 감지 장치
KR100383263B1 (ko) * 2001-03-19 2003-05-09 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 배치 방법
JP2003068880A (ja) * 2001-08-29 2003-03-07 Hitachi Ltd 半導体集積回路装置
KR100414203B1 (ko) * 2001-11-19 2004-01-13 삼성전자주식회사 상이한 열들의 인접한 비트 라인들 간의 커플링 노이즈를방지할 수 있는 반도체 메모리 장치
US20030214867A1 (en) * 2002-05-17 2003-11-20 Matthew Goldman Serially sensing the output of multilevel cell arrays
KR100490653B1 (ko) * 2002-10-31 2005-05-24 주식회사 하이닉스반도체 노이즈가 감소된 반도체 메모리 장치
JP4632287B2 (ja) 2003-10-06 2011-02-16 株式会社日立製作所 半導体集積回路装置

Also Published As

Publication number Publication date
US8022484B2 (en) 2011-09-20
JP2007122834A (ja) 2007-05-17
US20080290373A1 (en) 2008-11-27
CN1959837B (zh) 2010-06-09
KR20070046762A (ko) 2007-05-03
DE102006051154A1 (de) 2007-05-24
JP4781783B2 (ja) 2011-09-28
US20070253267A1 (en) 2007-11-01
US7423924B2 (en) 2008-09-09
KR100853335B1 (ko) 2008-08-21
CN1959837A (zh) 2007-05-09

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