JP2007019386A - 半導体チップの製造方法 - Google Patents
半導体チップの製造方法 Download PDFInfo
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- JP2007019386A JP2007019386A JP2005201536A JP2005201536A JP2007019386A JP 2007019386 A JP2007019386 A JP 2007019386A JP 2005201536 A JP2005201536 A JP 2005201536A JP 2005201536 A JP2005201536 A JP 2005201536A JP 2007019386 A JP2007019386 A JP 2007019386A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000227 grinding Methods 0.000 claims abstract description 20
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 claims description 20
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract description 8
- 239000007795 chemical reaction product Substances 0.000 abstract description 6
- 238000004380 ashing Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 16
- 239000007789 gas Substances 0.000 description 10
- 229910052731 fluorine Inorganic materials 0.000 description 8
- 239000011737 fluorine Substances 0.000 description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
【解決手段】半導体ウェハを個々の半導体装置毎に分割して半導体チップ1dを製造する半導体チップの製造方法において、半導体ウェハの分割をプラズマエッチングによって行うプラズマダイシングのために形成されたマスク3を、研削ヘッド26を用いた機械研削によって除去する。これにより、プラズマアッシングによってマスクを除去する場合に避けがたい反応生成物の発生を防止して、堆積したパーティクルによる品質劣化を生じることなくダイシングを行うことができる。
【選択図】図5
Description
により、マスク除去時の反応生成物の発生を防止して、堆積したパーティクルによる品質劣化を生じることなくダイシングを行うことができる。
理作用によってプラズマダイシングが行われる。
1a 半導体装置形成面
1d 半導体チップ
2 保護テープ
3 マスク
3a ストリートライン
10 ドライエッチング装置
Claims (2)
- ストリートラインによって区画された複数の領域のそれぞれに半導体装置が形成された半導体ウェハを個々の半導体装置毎に分割して半導体チップを製造する半導体チップの製造方法であって、
前記半導体ウェハの半導体装置形成面側に剥離可能な保護テープを貼付ける保護テープ貼付工程と、前記保護テープを貼り付けた半導体ウェハの裏面側を研削して半導体ウェハを薄化する裏面研削工程と、前記裏面研削工程の後、前記複数の領域を覆うマスクを半導体ウェハの裏面に形成するマスク形成工程と、前記マスクが形成された表面から半導体ウェハにプラズマを照射して前記半導体ウェハにおいてマスクで覆われていない部分を除去することにより、この半導体ウェハを個々の半導体装置毎に複数の半導体チップに分割するプラズマダイシング工程と、このプラズマダイシング工程後に前記マスクが形成された裏面を研削することにより前記マスクを除去するマスク除去工程と、前記マスク除去工程において前記裏面に形成された加工変質層を除去する加工変質層除去工程と、前記分割された複数の半導体チップから前記保護テープを剥離するテープ剥離工程とを含むことを特徴とする半導体チップの製造方法。 - 前記加工変質層除去工程において、前記裏面をプラズマエッチングすることにより前記裏面に形成された加工変質層を除去することを特徴とする請求項1記載の半導体チップの製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201536A JP4285455B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体チップの製造方法 |
PCT/JP2006/314114 WO2007007883A1 (en) | 2005-07-11 | 2006-07-10 | Manufacturing method of semiconductor devices |
US11/576,363 US7923351B2 (en) | 2005-07-11 | 2006-07-10 | Manufacturing method of semiconductor devices |
EP06781139A EP1797589A1 (en) | 2005-07-11 | 2006-07-10 | Manufacturing method of semiconductor devices |
CNB2006800010558A CN100456449C (zh) | 2005-07-11 | 2006-07-10 | 半导体器件的制造方法 |
KR1020077007704A KR20080015771A (ko) | 2005-07-11 | 2006-07-10 | 반도체 장치의 제조 방법 |
TW095125081A TW200741838A (en) | 2005-07-11 | 2006-07-10 | Manufacturing method of semiconductor chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201536A JP4285455B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体チップの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007019386A true JP2007019386A (ja) | 2007-01-25 |
JP4285455B2 JP4285455B2 (ja) | 2009-06-24 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005201536A Active JP4285455B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体チップの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7923351B2 (ja) |
EP (1) | EP1797589A1 (ja) |
JP (1) | JP4285455B2 (ja) |
KR (1) | KR20080015771A (ja) |
CN (1) | CN100456449C (ja) |
TW (1) | TW200741838A (ja) |
WO (1) | WO2007007883A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100828025B1 (ko) | 2007-06-13 | 2008-05-08 | 삼성전자주식회사 | 웨이퍼 절단 방법 |
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JP2016171262A (ja) * | 2015-03-13 | 2016-09-23 | 古河電気工業株式会社 | 半導体ウェハの処理方法、半導体チップおよび表面保護テープ |
JP2018093116A (ja) * | 2016-12-06 | 2018-06-14 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
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- 2006-07-10 TW TW095125081A patent/TW200741838A/zh unknown
- 2006-07-10 WO PCT/JP2006/314114 patent/WO2007007883A1/en active Application Filing
- 2006-07-10 EP EP06781139A patent/EP1797589A1/en not_active Withdrawn
- 2006-07-10 US US11/576,363 patent/US7923351B2/en active Active
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KR20170094301A (ko) * | 2015-03-13 | 2017-08-17 | 후루카와 덴키 고교 가부시키가이샤 | 반도체 웨이퍼의 처리 방법, 반도체 칩 및 표면 보호 테이프 |
US10418267B2 (en) | 2015-03-13 | 2019-09-17 | Furukawa Electric Co., Ltd. | Method of processing a semiconductor wafer, semiconductor chip, and surface protective tape |
KR102070031B1 (ko) | 2015-03-13 | 2020-01-29 | 후루카와 덴키 고교 가부시키가이샤 | 반도체 웨이퍼의 처리 방법, 반도체 칩 및 표면 보호 테이프 |
JP2018093116A (ja) * | 2016-12-06 | 2018-06-14 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
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EP1797589A1 (en) | 2007-06-20 |
US20090209087A1 (en) | 2009-08-20 |
JP4285455B2 (ja) | 2009-06-24 |
KR20080015771A (ko) | 2008-02-20 |
WO2007007883A1 (en) | 2007-01-18 |
US7923351B2 (en) | 2011-04-12 |
TW200741838A (en) | 2007-11-01 |
CN101044613A (zh) | 2007-09-26 |
CN100456449C (zh) | 2009-01-28 |
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