JP2012204588A - 半導体デバイスチップの実装方法 - Google Patents
半導体デバイスチップの実装方法 Download PDFInfo
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- JP2012204588A JP2012204588A JP2011067621A JP2011067621A JP2012204588A JP 2012204588 A JP2012204588 A JP 2012204588A JP 2011067621 A JP2011067621 A JP 2011067621A JP 2011067621 A JP2011067621 A JP 2011067621A JP 2012204588 A JP2012204588 A JP 2012204588A
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- semiconductor device
- wafer
- device chip
- electrodes
- protruding
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000012212 insulator Substances 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000002390 adhesive tape Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 description 48
- 238000000227 grinding Methods 0.000 description 20
- 239000002313 adhesive film Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- 239000002923 metal particle Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
【解決手段】複数の突起電極17を有する半導体デバイスチップを、配線基板又はウエーハ11上に実装する半導体デバイスチップの実装方法であって、半導体デバイスウエーハを用意するステップと、半導体デバイスウエーハの突起電極側を絶縁体で被覆して隣接する突起電極間に絶縁体を充填する絶縁体被覆ステップと、絶縁体が被覆された突起電極側を平坦化し、突起電極の端面を露出させる突起電極端面露出ステップと、半導体デバイスウエーハを個々の半導体デバイスチップに分割する分割ステップと、配線基板又はウエーハの電極と半導体デバイスチップの突起電極間に異方性導電体を介在させて半導体デバイスチップを配線基板又はウエーハ上に搭載し、電極と突起電極とを接続する実装ステップと、を具備したことを特徴とする。
【選択図】図5
Description
13 分割予定ライン(ストリート)
15 半導体デバイス(半導体デバイスチップ)
17 バンプ(突起電極)
10 NCF又はNCP
22 バイト
23 保護テープ
34 研削ホイール
38 研削砥石
40 切削ブレード
42 異方性導電フィルム(ACF)
44 配線基板
46 電極
T ダイシングテープ
F 環状フレーム
Claims (3)
- 複数の突起電極を有する半導体デバイスチップを、該突起電極に対応した電極を有する配線基板又はウエーハ上に実装する半導体デバイスチップの実装方法であって、
格子状に形成された複数の分割予定ラインで区画された各領域にそれぞれ複数の突起電極を有する半導体デバイスが形成された半導体デバイスウエーハを用意するステップと、
該半導体デバイスウエーハの該突起電極側を絶縁体で被覆して隣接する該突起電極間に該絶縁体を充填する絶縁体被覆ステップと、
該絶縁体が被覆された半導体デバイスウエーハの該突起電極側を平坦化するとともに該突起電極の端面を露出させる突起電極端面露出ステップと、
該半導体デバイスウエーハを該分割予定ラインに沿って個々の半導体デバイスチップに分割する分割ステップと、
該突起電極に対応した電極を有する配線基板又はウエーハの該電極と半導体デバイスチップの該突起電極間に異方性導電体を介在させて半導体デバイスチップを配線基板又はウエーハ上に搭載し、該電極と該突起電極とを接続する実装ステップと、
を具備したことを特徴とする半導体デバイスチップの実装方法。 - 複数の突起電極を有する半導体デバイスチップを、該突起電極に対応した電極を有する配線基板又はウエーハ上に実装する半導体デバイスチップの実装方法であって、
半導体デバイスチップの該突起電極側を絶縁体で被覆して隣接する該突起電極間に該絶縁体を充填する絶縁体被覆ステップと、
該絶縁体が被覆された半導体デバイスチップの該突起電極側を平坦化するとともに該突起電極の端面を露出させる突起電極端面露出ステップと、
該突起電極端面露出ステップを実施した後、該突起電極に対応した電極を有する配線基板又はウエーハの該電極と半導体デバイスチップの該突起電極間に異方性導電体を介在させて半導体デバイスチップを配線基板又はウエーハ上に実装し、該電極と該突起電極とを接続する実装ステップと、
を具備したことを特徴とする半導体デバイスチップの実装方法。 - 複数の半導体デバイスチップを粘着テープに貼着する貼着ステップを更に具備し、該突起電極端面露出ステップは複数の半導体デバイスチップが該粘着テープに貼着された状態で実施する請求項2記載の半導体デバイスチップの実装方法。
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JP2011067621A JP2012204588A (ja) | 2011-03-25 | 2011-03-25 | 半導体デバイスチップの実装方法 |
US13/423,454 US20120244663A1 (en) | 2011-03-25 | 2012-03-19 | Semiconductor device chip mounting method |
CN2012100778860A CN102693920A (zh) | 2011-03-25 | 2012-03-22 | 半导体器件芯片的安装方法 |
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JP2005294430A (ja) * | 2004-03-31 | 2005-10-20 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2006049482A (ja) * | 2004-08-03 | 2006-02-16 | Furukawa Electric Co Ltd:The | 半導体装置製造方法およびウエハ加工用テープ |
JP2006073995A (ja) * | 2004-08-05 | 2006-03-16 | Fujitsu Ltd | 基体の加工方法 |
JP2007019386A (ja) * | 2005-07-11 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体チップの製造方法 |
JP2009147231A (ja) * | 2007-12-17 | 2009-07-02 | Hitachi Chem Co Ltd | 実装方法、半導体チップ、及び半導体ウエハ |
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KR100382759B1 (ko) * | 1999-01-27 | 2003-05-09 | 시티즌 도케이 가부시키가이샤 | 이방성 도전 접착제를 이용한 반도체 장치의 실장 방법 |
US6717245B1 (en) * | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US7768125B2 (en) * | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
JP2009054920A (ja) * | 2007-08-29 | 2009-03-12 | Disco Abrasive Syst Ltd | 半導体ウェーハの加工方法 |
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JP2005294430A (ja) * | 2004-03-31 | 2005-10-20 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2006049482A (ja) * | 2004-08-03 | 2006-02-16 | Furukawa Electric Co Ltd:The | 半導体装置製造方法およびウエハ加工用テープ |
JP2006073995A (ja) * | 2004-08-05 | 2006-03-16 | Fujitsu Ltd | 基体の加工方法 |
JP2007019386A (ja) * | 2005-07-11 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体チップの製造方法 |
JP2009147231A (ja) * | 2007-12-17 | 2009-07-02 | Hitachi Chem Co Ltd | 実装方法、半導体チップ、及び半導体ウエハ |
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