JP2007005759A - 半導体素子及びその製造方法 - Google Patents
半導体素子及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 174
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 208000012868 Overgrowth Diseases 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000008569 process Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
【解決手段】半導体素子は、半導体基板201上に形成されて活性領域を提供し、側壁下部端に凹部が形成された半導体層203、204と、素子分離用の第1の絶縁膜202Aと、第1の絶縁膜202及び半導体層203、204の側壁に形成された素子分離用の第2の絶縁膜206とを備えている。半導体素子の製造方法は、半導体基板201の一部の領域を露出させた第1の絶縁膜202Aを形成するステップ、第1の半導体層203を形成するステップ、第2の半導体層204Aを形成するステップ、第2の半導体層204A及び第1の絶縁膜202Aを選択的にエッチングするステップ、第1の絶縁膜202Aを除去するステップ及び第2の絶縁膜206を形成するステップを含む。
【選択図】図2E
Description
202、202A、302 第1の絶縁膜
203、303 第1の半導体層
204、204A、304、304A 第2の半導体層
206、306 第2の絶縁膜
207、308 ゲート絶縁膜
208、309 ゲート導電膜
209、310 ゲートパターン
210、311 スペーサ
307 ボイド領域
Claims (20)
- 半導体基板上に形成されて活性領域を提供するとともに、側部下側に、側壁側に開口する複数の凹部が形成された半導体層と、
前記凹部に埋め込まれた素子分離用の第1の絶縁膜と、
前記第1の絶縁膜及び前記半導体層の側壁に形成された素子分離用の第2の絶縁膜と
を備えることを特徴とする半導体素子。 - 前記半導体層は、前記凹部間に形成された第1の半導体層と、該第1の半導体層上に形成され、該第1の半導体層より幅が広い第2の半導体層とで構成されていることを特徴とする請求項1に記載の半導体素子。
- 前記第1の半導体層は、SPE(Solid Phase Epitaxy)法またはSEG(Silicon Epitaxy Growth)法によって形成された単結晶シリコンで構成されていることを特徴とする請求項2に記載の半導体素子。
- 前記第2の半導体層は、ELO(Epitaxial Lateral Overgrowth)法により形成されたシリコンで構成されていることを特徴とする請求項2に記載の半導体素子。
- 前記第1の絶縁膜は、酸化物または窒化物で構成されていることを特徴とする請求項1に記載の半導体素子。
- 前記第2の絶縁膜は、CVD法により形成されたHDP(High Density Plasma)膜であることを特徴とする請求項1に記載の半導体素子。
- 半導体基板上に形成されて活性領域を提供するとともに、側部下側に、側壁側に開口する凹部が形成された半導体層と、
前記半導体層の上部側壁に整合して形成された素子分離用の絶縁膜と
を備えることを特徴とする半導体素子。 - 前記半導体層は、前記凹部間に形成された第1の半導体層と、前記第1の半導体層上に形成され、前記第1の半導体層より幅が広い第2の半導体層とで構成されていることを特徴とする請求項7に記載の半導体素子。
- 前記第1の半導体層は、SPE(Solid Phase Epitaxy)法またはSEG(Silicon Epitaxy Growth)法により形成された単結晶シリコンで構成されていることを特徴とする請求項8に記載の半導体素子。
- 前記第2の半導体層は、ELO(Epitaxial Lateral Overgrowth)法によって形成されたシリコンで構成されていることを特徴とする請求項8に記載の半導体素子。
- 前記絶縁膜は、CVD法によって形成されたHDP(High Density Plasma)膜であることを特徴とする請求項7に記載の半導体素子。
- 半導体基板の一部の領域を露出させた第1の絶縁膜を形成するステップと、
前記一部の領域に第1の半導体層を形成するステップと、
前記第1の半導体層及び前記第1の絶縁膜上に、第2の半導体層を形成するステップと、
該第2の半導体層及び前記第1の絶縁膜を選択的にエッチングするステップと、
前記第2の半導体層及び前記第1の絶縁膜の側壁に、第2の絶縁膜を形成するステップと
を含むことを特徴とする半導体素子の製造方法。 - 前記第1の半導体層は、SPE(Solid Phase Epitaxy)法またはSEG(Silicon Epitaxy Growth)法によって形成された単結晶シリコンで構成されていることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記第2の半導体層は、ELO(Epitaxial Lateral Overgrowth)法によって形成されたシリコンで構成されていることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記第1の絶縁膜は、酸化物または窒化物で構成されていることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記第2の絶縁膜は、CVD法で形成されたHDP(High Density Plasma)膜であることを特徴とする請求項12に記載の半導体素子の製造方法。
- 半導体基板の一部の領域を露出させた第1の絶縁膜を形成するステップと、
前記一部の領域に第1の半導体層を形成するステップと、
該第1の半導体層及び前記第1の絶縁膜上に、第2の半導体層を形成するステップと、
該第2の半導体層及び前記第1の絶縁膜を選択的にエッチングするステップと、
前記第1の絶縁膜を除去するステップと、
前記第2の半導体層の側壁に整合させて、第2の絶縁膜を形成するステップと
を含むことを特徴とする半導体素子の製造方法。 - 前記第1の半導体層は、SPE(Solid Phase Epitaxy)法またはSEG(Silicon Epitaxy Growth)法によって形成された単結晶シリコンで構成されていることを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記第2の半導体層は、ELO(Epitaxial Lateral Overgrowth)法によって形成されたシリコンで構成されていることを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記絶縁膜は、CVD法によって形成されたHDP(High Density Plasma)膜で構成されていることを特徴とする請求項17に記載の半導体素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2005-0055863 | 2005-06-27 | ||
KR1020050055863A KR100637692B1 (ko) | 2005-06-27 | 2005-06-27 | 반도체 소자 및 그 제조 방법 |
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JP2007005759A true JP2007005759A (ja) | 2007-01-11 |
JP5307971B2 JP5307971B2 (ja) | 2013-10-02 |
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JP2006014546A Expired - Fee Related JP5307971B2 (ja) | 2005-06-27 | 2006-01-24 | 半導体素子の製造方法 |
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US (2) | US7348255B2 (ja) |
JP (1) | JP5307971B2 (ja) |
KR (1) | KR100637692B1 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2008186838A (ja) * | 2007-01-26 | 2008-08-14 | Toshiba Corp | 半導体装置、その製造方法及び不揮発性半導体記憶装置 |
JP5315779B2 (ja) * | 2008-05-09 | 2013-10-16 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
Citations (10)
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JPH05175326A (ja) * | 1991-12-25 | 1993-07-13 | Rohm Co Ltd | 半導体装置およびその製法 |
JPH0846202A (ja) * | 1994-07-21 | 1996-02-16 | Lg Semicon Co Ltd | 半導体素子の製造方法 |
JPH0974189A (ja) * | 1995-09-06 | 1997-03-18 | Sharp Corp | 半導体装置の製造方法 |
JPH09219524A (ja) * | 1996-02-09 | 1997-08-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002190599A (ja) * | 2000-12-20 | 2002-07-05 | Toshiba Corp | 半導体装置及びその製造方法 |
US6429091B1 (en) * | 2000-12-08 | 2002-08-06 | International Business Machines Corporation | Patterned buried insulator |
JP2002237602A (ja) * | 2001-02-09 | 2002-08-23 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004296902A (ja) * | 2003-03-27 | 2004-10-21 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2004336052A (ja) * | 2003-05-02 | 2004-11-25 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
US20050133789A1 (en) * | 2003-12-19 | 2005-06-23 | Chang-Woo Oh | Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same |
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US6034417A (en) * | 1998-05-08 | 2000-03-07 | Micron Technology, Inc. | Semiconductor structure having more usable substrate area and method for forming same |
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JP3308245B2 (ja) | 1999-08-12 | 2002-07-29 | 住友ゴム工業株式会社 | 空気入りタイヤ |
KR100353468B1 (en) | 2000-12-26 | 2002-09-19 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
KR100403627B1 (ko) * | 2001-05-08 | 2003-10-30 | 삼성전자주식회사 | 트랜치 소자분리 방법 |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US6919258B2 (en) * | 2003-10-02 | 2005-07-19 | Freescale Semiconductor, Inc. | Semiconductor device incorporating a defect controlled strained channel structure and method of making the same |
US7029964B2 (en) * | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
-
2005
- 2005-06-27 KR KR1020050055863A patent/KR100637692B1/ko active IP Right Grant
- 2005-12-28 US US11/321,925 patent/US7348255B2/en active Active
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- 2006-01-24 JP JP2006014546A patent/JP5307971B2/ja not_active Expired - Fee Related
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2007
- 2007-12-04 US US11/999,466 patent/US20080087980A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05175326A (ja) * | 1991-12-25 | 1993-07-13 | Rohm Co Ltd | 半導体装置およびその製法 |
JPH0846202A (ja) * | 1994-07-21 | 1996-02-16 | Lg Semicon Co Ltd | 半導体素子の製造方法 |
JPH0974189A (ja) * | 1995-09-06 | 1997-03-18 | Sharp Corp | 半導体装置の製造方法 |
JPH09219524A (ja) * | 1996-02-09 | 1997-08-19 | Toshiba Corp | 半導体装置及びその製造方法 |
US6429091B1 (en) * | 2000-12-08 | 2002-08-06 | International Business Machines Corporation | Patterned buried insulator |
JP2002190599A (ja) * | 2000-12-20 | 2002-07-05 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002237602A (ja) * | 2001-02-09 | 2002-08-23 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004296902A (ja) * | 2003-03-27 | 2004-10-21 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2004336052A (ja) * | 2003-05-02 | 2004-11-25 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
US20050133789A1 (en) * | 2003-12-19 | 2005-06-23 | Chang-Woo Oh | Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same |
Also Published As
Publication number | Publication date |
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US20080087980A1 (en) | 2008-04-17 |
US7348255B2 (en) | 2008-03-25 |
KR100637692B1 (ko) | 2006-10-25 |
JP5307971B2 (ja) | 2013-10-02 |
US20060292819A1 (en) | 2006-12-28 |
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