JP2006093189A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2006093189A JP2006093189A JP2004273024A JP2004273024A JP2006093189A JP 2006093189 A JP2006093189 A JP 2006093189A JP 2004273024 A JP2004273024 A JP 2004273024A JP 2004273024 A JP2004273024 A JP 2004273024A JP 2006093189 A JP2006093189 A JP 2006093189A
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring board
- main surface
- semiconductor device
- external terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
【解決手段】 配線基板1の上面上にMPUが形成された半導体チップ2AとSDRAMが形成された半導体チップ2Bとを2段に積み重ねて実装し、これらの半導体2A,2Bをモールド樹脂3で封止したSiPにおいて、配線基板1の下面外周に半導体チップ2Aに電気的に接続された複数の電極5cをSiPの外部端子として配置し、配線基板1の下面の上記複数の電極5cの最も内側の配置列よりもさらに内側に、半導体チップ2Aと半導体チップ2Bとを電気的に接続する複数の配線12と電気的に接続された複数の電極5dをSDRAMの試験端子として設けた。
【選択図】 図9
Description
図1は本実施の形態の半導体装置の内部構成を示す配線基板の上面(第1主面)側の平面図、図2は図1の半導体装置の配線基板の下面(第2主面)の平面図、図3は図1および図2のY1−Y1線の断面図、図4は図1の半導体装置の第2半導体チップの主面の平面図、図5は図1の半導体装置の第1半導体チップの主面の平面図、図6は図5の第1半導体チップの端子の番号と名前の説明図、図7は図1の半導体装置の配線基板の最下の配線層面(第2主面)の平面図、図8は図1の半導体装置の配線基板の最上の配線層(第1主面)の一部の平面図である。
図19は本実施の形態2の半導体装置の下面の平面図、図20は図19のY2−Y2線の断面図、図21は図20の領域Rの拡大断面図、図22は図21の変形例の断面図である。
2A 半導体チップ(第2半導体チップ)
2B 半導体チップ(第1半導体チップ)
3 モールド樹脂(封止体)
4 半田バンプ(端子)
5a 電極(第2端子)
5b 電極(第1端子)
5c 電極(第1外部端子)
5d 電極(第2外部端子)
7 アンダーフィル樹脂
9 ボンディングパッド(端子)
11 ボンディングワイヤ
12 配線
13 接着剤
15 ソルダレジスト(絶縁層)
16 開口部
17a,17b 導体パターン
20 半田バンプ
21 外部LSI
25 マスキング層
26 プローブ
Claims (20)
- (a)第1主面およびその反対側の第2主面を有する配線基板と、
(b)前記配線基板の第1主面側に実装されたメモリ回路を有する第1半導体チップと、
(c)前記配線基板の第1主面側に実装され、前記メモリ回路を制御する回路を有する第2半導体チップと、
(d)前記配線基板の第1主面側に第1、第2半導体チップを封止するように設けられた封止体とを備え、
前記配線基板の第1主面には、前記第1半導体チップの複数の端子が電気的に接続された複数の第1端子と、前記第2半導体チップの複数の端子が電気的に接続された複数の第2端子とが配置されており、
前記配線基板の第2主面には、前記配線基板の内部の配線を通じて第2半導体チップに電気的に接続された複数の第1外部端子と、前記第1半導体チップおよび前記第2半導体チップを電気的に接続する前記配線基板内の複数の配線に電気的に接続された複数の第2外部端子とが配置されており、
前記複数の第1外部端子は、前記配線基板の第2主面の外周に沿って複数列を成すように配置されており、
前記複数の第2外部端子は、前記複数の第1外部端子の配置列の最も内側の配置列よりもさらに1配置列以上隔てた内側の領域に配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記複数の第2外部端子は、前記配線基板の第2主面の最表層に形成された絶縁層によって覆われていることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記絶縁層はソルダレジストであることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数の第2外部端子は、前記配線基板の第2主面の最表層に形成された絶縁層から露出されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記メモリ回路は、シンクロナスDRAMであることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記シンクロナスDRAMは、DDR−シンクロナスDRAMであることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数の第1外部端子には半田バンプが接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数の第1外部端子には半田バンプが接続され、前記複数の第2外部端子には半田バンプが接続されていないことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第2半導体チップと前記第1半導体チップとが積層されていることを特徴とする半導体装置。
- 請求項9記載の半導体装置において、
前記第2半導体チップは、前記第2半導体チップの複数の端子が複数の半田バンプを介して前記配線基板の第1主面の前記複数の第2端子と電気的に接続された状態で前記配線基板の第1主面上に実装されており、
前記第1半導体チップは、前記第2半導体チップ上に積層されており、前記第1半導体チップの複数の端子は複数のボンディングワイヤを介して前記配線基板の第1主面の前記複数の第1端子と電気的に接続されていることを特徴とする半導体装置。 - (a)第1主面およびその反対側の第2主面を有する配線基板と、
(b)前記配線基板の第1主面側に実装されたメモリ回路を有する第1半導体チップと、
(c)前記配線基板の第1主面側に実装され、前記メモリ回路を制御する回路を有する第2半導体チップと、
(d)前記配線基板の第1主面側に第1、第2半導体チップを封止するように設けられた封止体とを備え、
前記配線基板の第1主面には、前記第1半導体チップの複数の端子が電気的に接続された複数の第1端子と、前記第2半導体チップの複数の端子が電気的に接続された複数の第2端子とが配置されており、
前記配線基板の第2主面には、前記配線基板の内部の配線を通じて第2半導体チップに電気的に接続された複数の第1外部端子と、前記第1半導体チップおよび前記第2半導体チップを電気的に接続する前記配線基板内の複数の配線に電気的に接続された複数の第2外部端子とが配置されており、
前記複数の第1外部端子は、前記配線基板の第2主面の外周から内側に向かって複数列を成すように配置されており、
前記複数の第2外部端子は、前記複数の第1外部端子の配置列の最も内側の配置列よりもさらに1配置列以上隔てた内側の領域に配置されており、
前記第1半導体チップおよび前記第2半導体チップを電気的に接続する前記配線基板内の複数の配線は、前記第1半導体チップのメモリ回路と、前記メモリ回路を制御する前記第2半導体チップ内の回路とを電気的に接続するデータ線であることを特徴とする半導体装置。 - 請求項11記載の半導体装置において、前記複数の第2外部端子は、前記配線基板の第2主面の最表層に形成された絶縁層によって覆われていることを特徴とする半導体装置。
- 請求項12記載の半導体装置において、前記絶縁層はソルダレジストであることを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記複数の第2外部端子は、前記配線基板の第2主面の最表層に形成された絶縁層から露出されていることを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記メモリ回路は、シンクロナスDRAMであることを特徴とする半導体装置。
- 請求項15記載の半導体装置において、前記シンクロナスDRAMは、DDR−シンクロナスDRAMであることを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記複数の第1外部端子には半田バンプが接続されていることを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記複数の第1外部端子には半田バンプが接続され、前記複数の第2外部端子には半田バンプが接続されていないことを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記第2半導体チップと前記第1半導体チップとが積層されていることを特徴とする半導体装置。
- 請求項19記載の半導体装置において、前記複数の第2外部端子は、前記第1、第2半導体チップの平面領域よりも内側に配置されていることを特徴とする半導体装置。
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JP2004273024A JP4601365B2 (ja) | 2004-09-21 | 2004-09-21 | 半導体装置 |
US11/221,904 US7323773B2 (en) | 2004-09-21 | 2005-09-09 | Semiconductor device |
US11/946,581 US7652368B2 (en) | 2004-09-21 | 2007-11-28 | Semiconductor device |
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Also Published As
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US20060060959A1 (en) | 2006-03-23 |
JP4601365B2 (ja) | 2010-12-22 |
US7323773B2 (en) | 2008-01-29 |
US7652368B2 (en) | 2010-01-26 |
US20080083978A1 (en) | 2008-04-10 |
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