TW515057B - Stackable flip-chip ball grid array package body - Google Patents

Abstract

A kind of stackable flip-chip ball grid array package body is disclosed in the present invention. The package body contains an IC chip and a flip-chip substrate that has no recessed die cavity. On the upper surface of the substrate, plural bump pads (closer to the center) and a plurality of the first ball pads (closer to the outer periphery) are disposed. The substrate is provided with plural circuit vias and plural interconnects for electrically connecting with the bump pads, the first ball pads and the second ball pads. The IC chip is provided with plural bonding pads; and plural solder bumps or conductive polymer bumps are disposed between the bonding pads and the corresponding bump pads for electrically connecting the IC chip to the flip-chip substrate. The first ball pad position on the upper side of the package body corresponds to the second ball pad on the lower side of the package body; and plural balls are soldered and connected to each other between the first ball pad and the second ball pad. The first ball pad also can be connected to an attached device or a detecting apparatus. In addition, the second ball pad can be connected to an attached device or a printed circuit board.

Description

V. Description of the invention (1) Array (bal 1 a repeatable stack) The present invention provides a chip array (BGA) grid array (BGA) package, especially a stackable Flip-chip ball grid array package.

With the development of FfKLD materials, various light, thin, and short packages have been continuously developed. Chip-on-chip BGA packages are multiplexed in chip-on-chip BGA packages. The chip (^ ㈠ 不 腺 县 阴 拉 ", person μ /乃 1 Bad Ran 疋 Connected the bonding pad (、) to the seal (Wlre bond) to the seal, which was reversed and passed through the solder bumps, 兹, and soil. ≪ Sweat the leavesϋ Block bump or conductive polymer bump to connect to the package base, this flip-chip BGA package can increase circuit density and reduce parasitic effect of the circuit. However, for more High-speed and higher-density packaging needs' The current flip-chip BGA package still feels powerless, so it is necessary to develop a flip-chip BGA package with a higher packing density. I = Refer to Figure 1. A schematic cross-sectional view of a flip-chip ball grid array package. Figure 1 shows a conventional two-layer (two-layer) flip-chip BGA package, which mainly includes a package substrate 12 and an IC. A die 1 4 is fixed on the surface of the package substrate 12. The package substrate 1 2 includes two copper trace layers (Cu trace layers) 16 and 18 respectively provided on the upper and lower sides of the package substrate 12 and a plurality of circuit conduction (v 丨 a) 2 〇 used to connect the copper conductor layers 1 6 With copper wire layer 18. The flip-chip BGA package 10 further includes a bump pad.

515057 V. Description of the invention (2) pad) 2 2. A plurality of solder ball pads (s 0 1 derba 1 1 pad) 2 4 are respectively provided on the surfaces of copper wire layers 16 and 18, and two green paint layers ( solder masks 2 6 and 2 8 respectively cover the surfaces of the copper wire layers 16 and 18 other than the bump pads 2 2 and the solder ball pads 2 4. The bump pads 22 and the solder ball pads 24 are made on the surfaces of the copper wire layers 16 and 18, and the green paint layers 26 and 28 are used as the insulating layer. The surface of the 1C chip 14 is provided with A plurality of bonding pads 30 are formed. The positions of the bonding pads 30 correspond to the positions of the bump pads 22 of the package substrate 12. A flip-chip BGA package 10 is provided with a plurality of solder bumps (solder: r bumps) 32 'between the bonding pads 30 of the IC chip 14 and the bump pads 22 of the package substrate 12. Electrically connected to the IC chip 14. The gap between the package substrate 12 and the IC chip 14 may be filled with a bottom sealing layer (e ρ χ underfill 1 & 761 :) 34 as needed to protect the package body 10 from the influence of harsh environments. At the same time, the stress at the solder bump 3 2 connection is eliminated. After the flip-chip BGA package 10 is completed, a plurality of solder balls 36 are used to fix the flip-chip BGA package 10 on a printed circuit board (print circuit b ^ ard, PCB) 38 to make the flip-chip BGA package 10. 38 pieces of printed circuit board are electrically connected together. = As shown in Figure 1, ... The current from Qu Nai Khan ’s body is transmitted to the solder via the bump soldering pad 22 of the mounting substrate 12, and then to the tin via the copper layer L, the book conductor 20, the copper conductor, and the wire layer 18. Ball pad "on, most

515057 V. Description of the invention (3) The current output by the IC chip 14 after the ... is transmitted to the printed circuit 38 through the solder balls 36. The same 'printed circuit board 38 can also input current into the IC chip 14 through the same direction of the circuit board. For example, the currently used flip-chip BG A package 10 cannot be repeatedly stacked on top of other packages, so that the printed circuit board 38 can only be provided with a single-layer & BGA package 10. When the printed circuit board 38 is provided with many different functions of the "crystalline BGA package 10", each flip-chip BGA package 10 needs to occupy the area of the circuit board 38, so that the wiring board level (bold 1 eve 1) Dian / Baoxiong, Du can't go any further. In a high-speed circuit (in): (: 1 ^ 1: 1), if a variety of flip-chip 30-eight packages 10 are scattered on the printed circuit board 38, the synchronization of high-frequency signals (synchronization) It will be affected by the layout of the electronic circuit layout and cannot obtain the timing signal. At present, several repeatable stacking packaging structures have been invented and patented. For example: US Patent No. 5, 5 9 8, 0 3 3—The case proposes a micro-BGA stacking scheme, but the structure of the structure is to fix the IC chip with a wireb οnding method. US Patent No. 5 , 5 9 4, 2 7 5—In the case, another stackable BG A package structure is proposed, which also uses gold wire technology to fix 丨 (; chip 'and applied to S0J (small out-line J-lead ) In the field of packaging, 0 515057 V. Description of the invention (4) "-'' '~ --- Therefore, the main purpose of the present invention is a crystal ball grid package package. L dry town body to further enhance the seal of the wiring board level Gold setting and improve the synchronization of the high-frequency signal of the package. Refer to Figures 1 and 3 for the package that is sucked. Figure 2 is a schematic diagram of the two 40 s red fee package 40 of the invention. The ball grid array Π η is shown in the figure. The present invention is a re-stackable ball grid array (BGA) package 40. The flip-chip BGA substrate can be a two-layer board (1 Comment 0-1 & 761). 〇 or multi-layer board (1111111: Bu 1376; 〇 structure, in this article to explain the structure of a two-layer board flip-chip BGA package 40, but the invention can also be extended to four-layer board or other multi-layer board On the flip chip bga2 board package. &Amp; As shown in Figures 2 and 3, the flip chip BGA package 40 is mainly composed of a substrate 42 and a 1C wafer 44. The substrate 42 includes two copper wire layers (Cu trace layers) 46, 48 are respectively provided on the upper and lower sides of the substrate 42, and a plurality of circuit vias 50 are used to connect the copper wire layer 46 and the copper wire layer 48. The 1C chip 44 is a flip-chip (fl iP — chiP) method is fixed on the substrate 42, so the substrate 42 is not provided with a recessed die cavity ) 0 The substrate 42 may be a substrate (not shown) of a multi-chip module (mulchi-chiP module, MCM), that is, multiple wafers may be mounted on the same substrate at the same time. In order to simplify the description, The substrate 42 containing only one wafer 515057 is described in V. Description of Invention (5) 44 as an illustration. In addition, the flip-chip BGA package 40 can be equipped with passive components on the surface or inside of the substrate 42 according to different circuit designs, such as a resistor or capacitor on the top, bottom or inside of the substrate 42 (Capacitor). The surfaces of the copper wire layers 4 6 and 4 8 on the substrate 42 are respectively covered with a green paint layer 52 and a green paint layer 54. The thickness of the green paint layers 52 and 54 is usually between 15 and 30 μm. The total thickness of the substrate 42 after covering the green lacquer layers 5 2 and 5 4 is approximately 100˜100 μm. A plurality of openings are reserved on the surface of the green paint layer 52 for forming a plurality of bump pads 56 and a plurality of solder ball pads 5 8. Similarly, many openings are reserved on the surface of the green paint layer 54 to serve as a plurality of solder ball pads 60. Both the bump pads 56 and the solder ball pads 58 are located on the upper side of the substrate 42, and the solder ball pads 60 are located on the lower side of the substrate 42. In addition, the bump pads 56 are distributed within a predetermined area 62, and the solder ball pads 58 are distributed outside the predetermined area 62. The bump pad 5 6 usually forms an anti-tarnish layer on the surface of the exposed copper wire layer 46. For example, the surface of the exposed copper wire layer 4 6 is plated with a nickel / gold film, and the solder ball pad 5 8 and 60 are also often plated with a nickel / gold film on the surfaces of the exposed copper conductor layers 46 and 48, respectively. The pattern of the copper conductor layers 46 and 48 and the position of the circuit conduction 50 are appropriately designed to allow the bump pad 5 6 to be electrically connected to the solder ball pad 58 or the solder ball pad 60. 515057 5. Description of the invention (6) Generally speaking, the thickness of the 1C chip is between 125 and 30 0 " m, and a plurality of bonding pads 64 and bonding pads 6 are provided on the lower side of the IC chip 4 4 The position of 4 corresponds to the position of the bump pad 56 on the substrate 44. The IC chip 44 is fixed on a predetermined area 62 of the substrate 42 by a plurality of solder bumps or conductive polymer bumps 66, and the solder bumps or conductive polymer bumps 66 are provided on The IC pad 44 is electrically connected to the substrate 42 between the bonding pad 64 of the IC chip 44 and the bump pad 56 of the substrate 42. The gap distance (after bonding) between the substrate 42 and the 1C wafer 44 is about 30 to 80 / zm. At this time, an epoxy underfill process may be performed according to the needs of the flip-chip technology. A bottom sealing layer (under fi 1 1 layer) 6 8 fills the gap between the substrate 42 and the 1C chip 4 4 to protect the flip-chip BGA package 40 from the harsh environment and eliminate solder bumps 6 6 connections Where the stress. Please refer to FIG. 4, which is a schematic cross-sectional view of a flip-chip BGA package of the present invention when stacked. As shown in FIG. 4, the position of the solder ball pad 58a on the flip-chip B G A package 40a corresponds to the solder ball pad 60b on the lower side of the other flip-chip BGA package 40b. When the flip-chip BGA package 40b is stacked on the flip-chip BGA package 40a, the flip-chip BGA package 40b (the solder ball 6 8 has been planted on the solder ball pad 60b) is aligned with the flip-chip BGA below The package body 40 a is then subjected to solder re-flow to fix and electrically connect the flip-chip BG A package body 40 b.

Page 10 515057 V. Description of the invention (7) Using the same method, the flip-chip BGA package 40 can be stacked repeatedly, for example, another flip-chip BGA package can be stacked on the flip-chip BGA package 40b 40 ° Please refer to FIGS. 5 and 6, which are bottom views of the flip-chip BGA package 40 a of FIG. 4. Generally speaking, the number and arrangement of bump bonding pads 56 and solder ball bonding pads 5 8 and 60 of the flip chip BGA package 40 can be changed according to different circuit requirements. Taking the solder ball pad 60a at the bottom of the flip-chip BGA package 40a in FIG. 4 as an example, the arrangement of the solder ball pads 60a shown in FIG. 5 is a typical array, and the arrangement shown in FIG. It is changed according to the arrangement of Figure 5. Please refer to FIG. 7 and FIG. 8. FIG. 7 is a schematic cross-sectional view of the first embodiment of the flip-chip BGA package 40 according to the present invention. FIG. 8 is a bottom view of the flip-chip BGA package 40d as shown in FIG. As shown in FIG. 7, the flip-chip BGA package 40 d is fixed on a printed circuit board (not shown, below), and the flip-chip BGA package I 40 (1 is then sequentially stacked with the flip-chip BGA packages 40 b and 40 c. In order to increase the heat dissipation effect of the flip-chip BG A package 40 d, a plurality of solder ball pads 7 can be placed in the central part below the substrate 42 d. In this way, the IC chip 4 4 d The temperature can be conducted to the lower printed circuit board through the solder ball pad 7 〇 and the connected solder ball pad 6 8. Figure 8 shows an example of the relative position of the solder ball pad 〇 at the bottom of the substrate 4 2 d. Please Referring to Figures 9 to 14, Figures 9 to 14 are flip chip 515057 of the present invention. V. Description of the invention (8) A cross-sectional schematic diagram of a BGA package and an accessory component stacked. The flip chip BGA package 40 itself can be mutually In addition to stacking, it is also possible to open y into tin and 4 balls 6 8 on the solder ball pad 58 or solder ball 60 to connect an accessory component or other electronic components to meet Different needs of circuit designers. As shown in Figure 9, the flip-chip BGA package 40b stacked on top It can be used to stack an impedance termination device 72 on the surface. As shown in Figure 10, an impedance matcher 74 can be installed between the flip-chip bga package 40 and 4c. As shown in FIGS. 9 to 10, both the impedance termination matching device 72 and the impedance matching device 74 can be manufactured outside of a BGA substrate. The impedance termination matching device 72 and the impedance matching device 74 are various resistors, capacitors, and inductors. Components such as industrial devices and strip-lines are integrated into a circuit substrate 76 and a circuit substrate 78, respectively, or by using surface adhesion technology , 78 surface devices such as resistors, capacitors, inductors, etc. The impedance value of the impedance termination matching device 72 and the impedance matching device ^ is designed according to the requirements of the circuit, and is usually 28Ω or 50Ω. Impedance matching The functions of the device 74 include signal timing control, signal noise reduction, and fine impedance control. ^ Figure 11 It is shown that on the uppermost flip-chip BGA package 40b, various different ball grid array (BG A) packages are stacked or have specific functions 515057 V. Description of the invention (9) 1C circuit, Figure 10. One shows a different size BGA package 80. In addition, 'the top BGA package for women's clothing can choose the conventional flip-chip BGA package 10 which does not stack functions, or other conventional type (Gold wire = bond) BGA package or package using other ball grid arrays, such as stacking an opening with ten openings down / mounting (not shown). Cavity-down BGA package As shown in Figure 12, the flip-chip BGA package 40b can be connected to a flex-board 82 to connect other external circuits. As shown in FIG. 13, the flip-chip BGA package 40 b can also be connected with a heat dissipation device 4 to improve the heat dissipation effect. The heat dissipating device 84 can be manufactured as a bga substrate (not shown), or it can be made as a metal (copper) scatter sheet as shown in Figure 13 or other types of heat dissipating wings (not shown). As shown in FIG. 14, the solder ball pads 58b = j on the flip-chip BGA package 40b are used to connect a detection device 86 to facilitate circuit testing. The detection device 86 includes a tester head 88 and a plurality of pogo pins 90. The tester head 88 is provided under the test probe head 88 and can be in contact with the solder ball 58b to form an electrical connection. The various accessory components listed above can also be applied to flip-chip BGA packages through appropriate = cascading. For example, the impedance matching device 72 in FIG. 9 may be installed on the flip-chip bga package 40c in FIG. 10, and the heat dissipation device 84 in FIG. 12 may also be installed in the impedance termination matching in FIG. 515. Instructions (ίο) on device 72. In addition, the flip-chip BGA package 40a in FIGS. 9 to 14 can be further stacked with other flip-chip BGA packages 40 and auxiliary components, and finally mounted on a printed circuit board (not shown), such as a motherboard ( mother board) or a daughter card. In order to simplify the illustration, the above-mentioned schematic diagrams of the flip-chip BG A packages 40a, 40b, 40c, 40d when stacked do not show the internal structure of the flip-chip BGA packages 40a, 40b, 40c, 40d. That is, its internal structure can be a two-layer board, a four-layer board or other multi-layer boards. Please refer to FIG. 15, which is a schematic cross-sectional view of a second embodiment of a flip-chip BGA package according to the present invention. Figure 15 shows a four-layer flip-chip BGA · | package 92, which has the same appearance as the two-layer flip-chip BGA package 40, but the substrate 42 also contains at least one copper wire layer 94 (in the figure The fifteenth middle is two inner copper wire layers 9 4). The copper wire layers 46 and 48 of the substrate 42 and the inner copper wire layer 94 and the circuit conduction 50 can be electrically connected to the bump pads 56 of the substrate 42 and the solder ball pads 58 and 60 through proper connection. Similarly, the application of the two-layer flip-chip BGA package 40 mentioned above can also be extended to the flip-chip bgA package 92 of a four-layer board or the flip-chip BGa package of another multilayer board. I—Please refer to FIG. 16. FIG. 16 is a stacking diagram of a third embodiment of a flip-chip BGA package according to the present invention. As shown in FIG. 16, the flip-chip BG A package 96 according to the third embodiment of the present invention is also mainly composed of a substrate 98 and a c-chip 100. The flip-chip BGA package 96 and flip-chip The% A package 40 is different in that the wafer 100 is fixed below the substrate 98. The rest of the flip-chip BGA package 96 515057 5. The structure of the invention (11), or the way it is connected to other components, can be applied in combination with the aforementioned flip-chip B G A package 40. The structure of the substrate 98 of the BGA package 96 and the substrate 42 of the BGA package 40 are very similar, neither of which is provided with a wafer fixing cavity, and the substrate 98 is provided with two steel wire layers 1 and 2 on the upper and lower sides. 0, 4, the inside of the substrate 98 is provided with a plurality of circuit conduction (not shown) to connect the copper wire layer 10 and the copper wire layer 104. At least one inner copper wire layer (not shown) may be provided inside the substrate 98 to electrically connect the circuit, the copper wire layer 102, and the copper wire layer 104. The surfaces of the copper wire layers 102 and 104 are respectively covered with two green paint layers 106 and 108. The green paint layer 10 on the upper side of the substrate 9 8 is provided with a plurality of solder ball pads II 0, and the green paint layer 1 0 8 on the lower side of the substrate 9 8 is provided with a plurality of solder ball pads 11 2 and a plurality of solder pads. Bump pads 11 4. The bump π 4 is distributed in a predetermined area (not shown) under the substrate, and the solder ball n 2 is distributed outside the predetermined area. A plurality of bonding pads (not shown) are provided on the lower side of the IC chip 100, and the positions thereof correspond to the positions of the bump pads 114 on the substrate 98. The wafer c is fixed on the lower side of the substrate 98 by using a plurality of solder bumps or conductive polymer bumps i6, and the IC wafer 100 is electrically connected to the substrate 98. An additional bottom sealing layer (not shown) may be filled between the wafer chip worker 0 and the substrate 98 to fill the gap between the IC wafer 100 and the substrate 98. 515057 5. Description of the invention (12) The solder ball pad n on the upper side of the flip-chip BGA package 96 a solder ball pad on the lower side of the flip-chip BGA package 96 " 2, and H 22 U0 and the corresponding tin A plurality of solder J pads are formed between the ball pads 112 to repeatedly stack the flip-chip BGA package 96. A plurality of solder balls (not shown) are provided on the upper side of the substrate 98, and these solders are connected to other packages or components, but are used to increase the substrate: 2 ::

1Mb, the solder ball pads 1 10 on the top of the crystal BGA package 96 can be connected to an impedance terminal matching device, an impedance matching device, a flexible board device, a heat sink or Other ball grid arrays are shown (t 沬). The solder ball pad 110 can also be directly electrically connected to a detection device (not groove = j, which contains at least one probe or a test probe head to contact the solder ball 10). The flip-chip BG A package 9 6 The solder ball pad i 丨 2 on the lower side can also be connected to an impedance matching device or a printed circuit board (not shown) by solder ball 118. The printed circuit board can be a motherboard or an add-in The characteristics of the invented flip-chip BGA packages 40, 92, and 96 are that they can be combined with other accessory components. Therefore, in the high-speed memory mode, q Wigh speed memory module, the flip-chip BGA Package 40. The package provides a high-density packaging structure. Because the flip-chip MA body 40, 92, 96 can greatly reduce the area occupied on the printed circuit board and shorten the distance of signal transmission. For system designers, flip chip

Page 16 515057 V. Description of the invention (13) BGA package 4 0, 9 2, 9 6 can be used as a high-speed hardware platform. For IC designers, flip chip BG A package 4 0, 9 2.96 can provide a better timing constraint margin, and can be widely used in high speed memory chips or parallel / z-processors. Compared with the conventional flip-chip BG A package 10, the flip-chip BG A package 40, 9 2, 9 6 has a repeatable stacking function, and can use a small printed circuit board area to install a multilayer flip-chip BG A package. The body 40, 92, 96 or other accessory components are used to increase the package density of the board level. At the same time, on high-speed circuits, the flip-chip A packages 40, 9, 2, 9 are connected in a corresponding manner, so the synchronization of high-frequency signals (synchr ο nizati 〇η) is not easily affected by the electronic circuit layout on the printed circuit board. (Lay out), and can improve the synchronization of high-frequency signal timing. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. Called melon

515057 Brief description of the diagrams Brief description of the diagrams Figure 1 is a schematic cross-sectional view of a conventional flip chip array package. Figure 2 is a schematic diagram of a two-layer flip-chip ball grid array package according to the present invention (take two-layer board as an example). Fig. 3 is a schematic cross-sectional view of the flip-chip ball grid array package shown in Fig. 2 (taking a two-layer board as an example). FIG. 4 is a schematic cross-sectional view of a flip-chip BGA package according to the present invention when stacked. Figures 5 and 6 are bottom views of the flip-chip BGA package of Figure 4 (two different examples). FIG. 7 is a schematic cross-sectional view of a first embodiment of a flip-chip BGA package according to the present invention. FIG. 8 is a bottom view of the flip-chip BGA package as shown in FIG. 7. Figures 9 to 14 are schematic cross-sectional views of a flip-chip BGA package according to the present invention when stacked with an accessory component. FIG. 15 is a schematic cross-sectional view of a second embodiment of a flip-chip BGA package according to the present invention. FIG. 16 is a schematic stacking diagram of a third embodiment of a flip-chip BGA package according to the present invention. Explanation of symbols in the figure 40, 40a, 40b, 40c, 40d Two-layer board flip-chip BGA package

Page 18 515057 Brief description of the diagram 42 '42a, 40d 4 [44dIC 46 Copper wire layer 48 50 Circuit continuity 52 54 Green paint layer 56 58 ^ 58a, 58b 60 ^ 6 0 a, 6 0 b 62 Predetermined area 64 66 Solder Bump 68 70 Solder ball solder pad 72 74 Impedance matching device 76 78 Circuit board 80 82 Flexible board device 84 86 Detection device 88 90 Probe 92 94 Inner copper conductive layer 96 98 Substrate 100 102 Copper wire layer 104 106 Green paint layer 108 110 solder ball pad 112 114 bump pad 116 substrate 5 chip copper wire layer green paint layer bump pad solder ball solder pad solder ball solder pad impedance terminal matching device circuit board 2 BGA substrate heat sink ( Thermal BGA substrate) Test probe head Four-layer board flip-chip BGA package flip-chip BGA package (another example) 1C chip copper wire layer green paint layer solder ball pad solder bump or conductive polymer bump 1 1 8 solder ball

Claims (1)

515057 6. Scope of patent application 1. A repeatable stackable f 1 ip_chip bal 1 grid array (BGA) package, which includes: a substrate, which includes a substrate The first surface and a second surface are not provided with a recessed die cavity; a plurality of solder bump pads are provided on the first surface of the substrate and are distributed on at least one predetermined surface. Within the area; a plurality of first solder ball pads are provided on the first surface of the substrate and are distributed outside the predetermined area; a plurality of second solder ball pads are provided on the substrate On the second surface; a plurality of circuit vias are provided inside the substrate for electrically connecting the plurality of bump pads, the plurality of first solder ball pads and the plurality of second solder ball pads And at least one IC chip (die) is provided on a predetermined area of the substrate, and a plurality of bonding pads (dock ^ padding) are provided on the lower side of the 1 C chip, and the positions of the plurality of f bonding pads and the Corresponding positions of a plurality of bump pads And a plurality of solder bumps or conductive polymer bumps are provided between the plurality of bonding pads and the corresponding bump pads, for fixing the IC chip; Wherein, the positions of the plurality of first solder ball pads of the package body correspond to ^ one of the plurality of second solder ball pads of the package body, and the plurality of first solder ball pads may correspond to the corresponding plural numbers. A plurality of solder balls are formed between the second solder ball pads to repeatedly stack the package. 2 · The package according to item 1 of the patent application scope, wherein the substrate further comprises Page 20 515057 6. Application scope At least one inner copper wire layer is provided inside the substrate, and the inner copper wire layer and the plurality of circuit continuities are used to electrically connect the plurality of first solder ball pads, the plurality of first Two solder ball pads and the plurality of bump pads. 3 · If the package of the first scope of the patent application, there is an underf i 1 1 layer between the IC chip and the substrate, and fill the gap between the IC chip and the substrate . 4 · For the package of item 1 in the scope of patent application, the central part of the second surface of the substrate is additionally provided with a plurality of third solder ball pads to increase the heat dissipation effect of the substrate. 5. For example, the package of the first scope of the patent application, wherein the surfaces of the plurality of first solder ball pads are further provided with a plurality of solder balls for connecting a first accessory component ° 6 · Such as The package of claim 5 in which the first accessory element is an impedance terminator. 7. The package of claim 5 in which the first accessory element is an impedance matcher. 8 · For the package according to item 5 of the patent application, wherein the first accessory component is a flex-board. M5057 on page 21 6. The scope of patent application "==== Encapsulation Zhao 'in which the-subordinate element is encapsulation Zhao' in which the-subordinate element is a plurality of eleventh. Package, in which the solder ball pad can be connected to a detection device. 1 2 · The package of item No.! In the scope of patent application, wherein a plurality of solder balls are provided on the surface of the plurality of second solder balls. , Used to connect a second accessory component or a printed circuit board (pcB). 13. The package according to item 12 of the patent application, wherein the second accessory component is an impedance matching device (impedance matcher). 1 4 · If the package of item 12 of the patent scope is claimed, wherein the printed circuit board is a mother board. 15. If the package of item 12 of the patent scope is applied, the printed circuit The board is a daughter card. 16. If the seal body of item 1 of the patent application scope, wherein the first surface is 515057 6. Scope of patent application The surface on the upper side of the substrate, and the second surface is the surface on the lower side of the substrate. 1 7. The package of claim 1, wherein the first surface is a surface on a lower side of the substrate, and the second surface is a surface on an upper side of the substrate.