JP2006041526A5 - - Google Patents

Download PDF

Info

Publication number
JP2006041526A5
JP2006041526A5 JP2005213971A JP2005213971A JP2006041526A5 JP 2006041526 A5 JP2006041526 A5 JP 2006041526A5 JP 2005213971 A JP2005213971 A JP 2005213971A JP 2005213971 A JP2005213971 A JP 2005213971A JP 2006041526 A5 JP2006041526 A5 JP 2006041526A5
Authority
JP
Japan
Prior art keywords
layer
semiconductor
crystal orientation
epitaxially grown
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005213971A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006041526A (ja
JP5044808B2 (ja
Filing date
Publication date
Priority claimed from US10/902,557 external-priority patent/US7253034B2/en
Application filed filed Critical
Publication of JP2006041526A publication Critical patent/JP2006041526A/ja
Publication of JP2006041526A5 publication Critical patent/JP2006041526A5/ja
Application granted granted Critical
Publication of JP5044808B2 publication Critical patent/JP5044808B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005213971A 2004-07-29 2005-07-25 集積半導体構造の形成方法（二重ｓｉｍｏｘハイブリッド配向技術（ｈｏｔ）基板） Expired - Fee Related JP5044808B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/902,557 US7253034B2 (en) 2004-07-29 2004-07-29 Dual SIMOX hybrid orientation technology (HOT) substrates
US10/902557 2004-07-29

Publications (3)

Publication Number Publication Date
JP2006041526A JP2006041526A (ja) 2006-02-09
JP2006041526A5 true JP2006041526A5 (enExample) 2008-07-17
JP5044808B2 JP5044808B2 (ja) 2012-10-10

Family

ID=35732872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005213971A Expired - Fee Related JP5044808B2 (ja) 2004-07-29 2005-07-25 集積半導体構造の形成方法（二重ｓｉｍｏｘハイブリッド配向技術（ｈｏｔ）基板）

Country Status (4)

Country Link
US (1) US7253034B2 (enExample)
JP (1) JP5044808B2 (enExample)
CN (1) CN100370601C (enExample)
TW (1) TWI349972B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119943A (ja) * 2002-09-30 2004-04-15 Renesas Technology Corp 半導体ウェハおよびその製造方法
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
JP2006210432A (ja) * 2005-01-25 2006-08-10 Nec Electronics Corp 基板の製造方法
US7358164B2 (en) * 2005-06-16 2008-04-15 International Business Machines Corporation Crystal imprinting methods for fabricating substrates with thin active silicon layers
US7473985B2 (en) * 2005-06-16 2009-01-06 International Business Machines Corporation Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
US7439108B2 (en) * 2005-06-16 2008-10-21 International Business Machines Corporation Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
US7344962B2 (en) * 2005-06-21 2008-03-18 International Business Machines Corporation Method of manufacturing dual orientation wafers
JP4566141B2 (ja) 2005-07-06 2010-10-20 株式会社リコー 設置角度調整装置及び設置角度調整方法
KR100655437B1 (ko) * 2005-08-09 2006-12-08 삼성전자주식회사 반도체 웨이퍼 및 그 제조방법
US20070040235A1 (en) 2005-08-19 2007-02-22 International Business Machines Corporation Dual trench isolation for CMOS with hybrid orientations
US7250656B2 (en) 2005-08-19 2007-07-31 International Business Machines Corporation Hybrid-orientation technology buried n-well design
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7396407B2 (en) * 2006-04-18 2008-07-08 International Business Machines Corporation Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
US7820501B2 (en) * 2006-10-11 2010-10-26 International Business Machines Corporation Decoder for a stationary switch machine
US20080169535A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Sub-lithographic faceting for mosfet performance enhancement
US7393738B1 (en) * 2007-01-16 2008-07-01 International Business Machines Corporation Subground rule STI fill for hot structure
US8016941B2 (en) * 2007-02-05 2011-09-13 Infineon Technologies Ag Method and apparatus for manufacturing a semiconductor
US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
FR2915318B1 (fr) * 2007-04-20 2009-07-17 St Microelectronics Crolles 2 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
FR2917235B1 (fr) 2007-06-06 2010-09-03 Soitec Silicon On Insulator Procede de realisation de composants hybrides.
US7989306B2 (en) * 2007-06-29 2011-08-02 International Business Machines Corporation Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
US8803195B2 (en) * 2007-08-02 2014-08-12 Wisconsin Alumni Research Foundation Nanomembrane structures having mixed crystalline orientations and compositions
US8039401B2 (en) * 2007-12-14 2011-10-18 Fairchild Semiconductor Corporation Structure and method for forming hybrid substrate
US8274115B2 (en) * 2008-03-19 2012-09-25 Globalfoundries Singapore Pte. Ltd. Hybrid orientation substrate with stress layer
US7528027B1 (en) 2008-03-25 2009-05-05 International Business Machines Corporation Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
FR2954584B1 (fr) * 2009-12-22 2013-07-19 Commissariat Energie Atomique Substrat hybride a isolation amelioree et procede de realisation simplifie d'un substrat hybride
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
DE102019100312A1 (de) * 2019-01-08 2020-07-09 Parcan NanoTech Co. Ltd. Substrat für eine kontrollierte lonenimplantation und Verfahren zur Herstellung eines Substrats für eine kontrollierte lonenimplantation

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US5173446A (en) * 1988-06-28 1992-12-22 Ricoh Company, Ltd. Semiconductor substrate manufacturing by recrystallization using a cooling medium
JPH04372166A (ja) * 1991-06-21 1992-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3017860B2 (ja) * 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
US5610083A (en) * 1996-05-20 1997-03-11 Chartered Semiconductor Manufacturing Pte Ltd Method of making back gate contact for silicon on insulator technology
US5888872A (en) * 1997-06-20 1999-03-30 Advanced Micro Devices, Inc. Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
US6214694B1 (en) * 1998-11-17 2001-04-10 International Business Machines Corporation Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
JP2001338988A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
JP3943932B2 (ja) * 2001-12-27 2007-07-11 株式会社東芝 半導体装置の製造方法
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US20030194846A1 (en) * 2002-04-11 2003-10-16 International Business Machines Corp. Medium dose simox over a wide BOX thickness range by a multiple implant, multiple anneal process
JP2004014856A (ja) * 2002-06-07 2004-01-15 Sharp Corp 半導体基板の製造方法及び半導体装置の製造方法
JP4294935B2 (ja) * 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6830962B1 (en) * 2003-08-05 2004-12-14 International Business Machines Corporation Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
US7023055B2 (en) * 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US6949420B1 (en) * 2004-03-12 2005-09-27 Sony Corporation Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US7291886B2 (en) * 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7094634B2 (en) * 2004-06-30 2006-08-22 International Business Machines Corporation Structure and method for manufacturing planar SOI substrate with multiple orientations
JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device

Similar Documents

Publication Publication Date Title
US6717213B2 (en) Creation of high mobility channels in thin-body SOI devices
US7528056B2 (en) Low-cost strained SOI substrate for high-performance CMOS technology
US9355887B2 (en) Dual trench isolation for CMOS with hybrid orientations
US9275910B2 (en) Semiconductor-on-insulator structure and method of fabricating the same
US7253034B2 (en) Dual SIMOX hybrid orientation technology (HOT) substrates
JP2007511068A5 (enExample)
TW202429726A (zh) 用於功率及rf應用的工程基板結構
TWI278941B (en) Thin channel MOSFET with source/drain stressors
US20080029815A1 (en) Semiconductor-on-insulator (SOI) strained active area transistor
JP2011522432A (ja) 基板上にゲルマニウム層を含む構造の製造プロセス
US7485929B2 (en) Semiconductor-on-insulator (SOI) strained active areas
CN1624921A (zh) 使用硅－硅直接晶片键合、在具有不同晶向的混合衬底上的cmos
JP2003078116A (ja) 半導体部材の製造方法及び半導体装置の製造方法
JP4322706B2 (ja) 半導体装置の製造方法
JP4609026B2 (ja) Ｓｏｉウェーハの製造方法
KR100704146B1 (ko) Ｓｏｉ 기판의 제조방법
KR100609367B1 (ko) Ｓｏｉ 기판의 제조방법
KR20240022780A (ko) 반도체 장치의 제조 방법
EP1900037A1 (en) Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
CN111029295A (zh) 一种具有浅沟槽隔离的soi结构及制备方法
JPS61154045A (ja) 半導体装置の製造方法
TW200839887A (en) Method of manufacturing semiconductor MOS transistor devices
JP2005259998A (ja) 半導体装置及びその製造方法