JP5044808B2 - 集積半導体構造の形成方法（二重ｓｉｍｏｘハイブリッド配向技術（ｈｏｔ）基板） - Google Patents

集積半導体構造の形成方法（二重ｓｉｍｏｘハイブリッド配向技術（ｈｏｔ）基板） Download PDF

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JP5044808B2
JP5044808B2 JP2005213971A JP2005213971A JP5044808B2 JP 5044808 B2 JP5044808 B2 JP 5044808B2 JP 2005213971 A JP2005213971 A JP 2005213971A JP 2005213971 A JP2005213971 A JP 2005213971A JP 5044808 B2 JP5044808 B2 JP 5044808B2
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layer
semiconductor
substrate
semiconductor layer
epitaxially grown
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JP2006041526A5 (enExample
JP2006041526A (ja
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ケビン・ケイ・チャン
ソウザ ジョエル・ピー・デ
アレキサンダー・レツニセク
デベンドラ・ケイ・サダナ
キャサリン・エル・ゼンガー
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2005213971A 2004-07-29 2005-07-25 集積半導体構造の形成方法（二重ｓｉｍｏｘハイブリッド配向技術（ｈｏｔ）基板） Expired - Fee Related JP5044808B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/902,557 US7253034B2 (en) 2004-07-29 2004-07-29 Dual SIMOX hybrid orientation technology (HOT) substrates
US10/902557 2004-07-29

Publications (3)

Publication Number Publication Date
JP2006041526A JP2006041526A (ja) 2006-02-09
JP2006041526A5 JP2006041526A5 (enExample) 2008-07-17
JP5044808B2 true JP5044808B2 (ja) 2012-10-10

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Country Link
US (1) US7253034B2 (enExample)
JP (1) JP5044808B2 (enExample)
CN (1) CN100370601C (enExample)
TW (1) TWI349972B (enExample)

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US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
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US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
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US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
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US7989306B2 (en) * 2007-06-29 2011-08-02 International Business Machines Corporation Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
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Also Published As

Publication number Publication date
TW200610063A (en) 2006-03-16
TWI349972B (en) 2011-10-01
JP2006041526A (ja) 2006-02-09
CN1728362A (zh) 2006-02-01
US20060024931A1 (en) 2006-02-02
US7253034B2 (en) 2007-08-07
CN100370601C (zh) 2008-02-20

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