TWI349972B - Dual simox hybrid orientation technology (hot) substrates - Google Patents

Dual simox hybrid orientation technology (hot) substrates

Info

Publication number
TWI349972B
TWI349972B TW094121129A TW94121129A TWI349972B TW I349972 B TWI349972 B TW I349972B TW 094121129 A TW094121129 A TW 094121129A TW 94121129 A TW94121129 A TW 94121129A TW I349972 B TWI349972 B TW I349972B
Authority
TW
Taiwan
Prior art keywords
simox
substrates
dual
hot
hybrid orientation
Prior art date
Application number
TW094121129A
Other languages
English (en)
Chinese (zh)
Other versions
TW200610063A (en
Inventor
Kevin K Chan
Joel P De Souza
Alexander Reznicek
Devendra K Sadana
Katherine L Saenger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200610063A publication Critical patent/TW200610063A/zh
Application granted granted Critical
Publication of TWI349972B publication Critical patent/TWI349972B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
TW094121129A 2004-07-29 2005-06-24 Dual simox hybrid orientation technology (hot) substrates TWI349972B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/902,557 US7253034B2 (en) 2004-07-29 2004-07-29 Dual SIMOX hybrid orientation technology (HOT) substrates

Publications (2)

Publication Number Publication Date
TW200610063A TW200610063A (en) 2006-03-16
TWI349972B true TWI349972B (en) 2011-10-01

Family

ID=35732872

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094121129A TWI349972B (en) 2004-07-29 2005-06-24 Dual simox hybrid orientation technology (hot) substrates

Country Status (4)

Country Link
US (1) US7253034B2 (enExample)
JP (1) JP5044808B2 (enExample)
CN (1) CN100370601C (enExample)
TW (1) TWI349972B (enExample)

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US7358164B2 (en) * 2005-06-16 2008-04-15 International Business Machines Corporation Crystal imprinting methods for fabricating substrates with thin active silicon layers
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KR100655437B1 (ko) * 2005-08-09 2006-12-08 삼성전자주식회사 반도체 웨이퍼 및 그 제조방법
US20070040235A1 (en) 2005-08-19 2007-02-22 International Business Machines Corporation Dual trench isolation for CMOS with hybrid orientations
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US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7396407B2 (en) * 2006-04-18 2008-07-08 International Business Machines Corporation Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
US7820501B2 (en) * 2006-10-11 2010-10-26 International Business Machines Corporation Decoder for a stationary switch machine
US20080169535A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Sub-lithographic faceting for mosfet performance enhancement
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US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
FR2915318B1 (fr) * 2007-04-20 2009-07-17 St Microelectronics Crolles 2 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
FR2917235B1 (fr) 2007-06-06 2010-09-03 Soitec Silicon On Insulator Procede de realisation de composants hybrides.
US7989306B2 (en) * 2007-06-29 2011-08-02 International Business Machines Corporation Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
US8803195B2 (en) * 2007-08-02 2014-08-12 Wisconsin Alumni Research Foundation Nanomembrane structures having mixed crystalline orientations and compositions
US8039401B2 (en) * 2007-12-14 2011-10-18 Fairchild Semiconductor Corporation Structure and method for forming hybrid substrate
US8274115B2 (en) * 2008-03-19 2012-09-25 Globalfoundries Singapore Pte. Ltd. Hybrid orientation substrate with stress layer
US7528027B1 (en) 2008-03-25 2009-05-05 International Business Machines Corporation Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
FR2954584B1 (fr) * 2009-12-22 2013-07-19 Commissariat Energie Atomique Substrat hybride a isolation amelioree et procede de realisation simplifie d'un substrat hybride
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
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US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
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Also Published As

Publication number Publication date
TW200610063A (en) 2006-03-16
JP2006041526A (ja) 2006-02-09
CN1728362A (zh) 2006-02-01
US20060024931A1 (en) 2006-02-02
US7253034B2 (en) 2007-08-07
CN100370601C (zh) 2008-02-20
JP5044808B2 (ja) 2012-10-10

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